• Korean Journal of Medicinal Crop Science
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• v.6 no.3
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• pp.216-220
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• 1998

The objectives of this study were to evaluate the effects of some seed pretreatments on seed germination, emergence, growth and yield of Bupleurum falcatum L. Seed treatments included stratification in open-field during winter, washing with running water, low temperature storage, soaking into $H_2SO_4$ solution, and scarification. Germination increased 15% by stratification and 9% by washing treatment compared to non-treatment, control. It was suggested that washing treatment leached inhibiting substance, while stratification treatment leached inhibiting substance and promoted growth of immatured embryo. In the field mulched with rice straw, stratification and washing treatments were effective to shorten days to emergence by 31 and 21 days and to increase emergence rate by 7 and 5 %, respectively, compared with control. By these two treatments, root growth was improved, the number of harvested plants was increased considerably and dry root yield per ha were increased by 29 and 22 %, respectively, compared with control.

• The Korean Journal of Pesticide Science
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• v.12 no.2
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• pp.177-183
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• 2008

For the development of integrated pest management system by harmonizing biological and chemical control, some experiments were carried out to select low toxic pesticides against natural enemies. Leaf dipping method, body dipping method, and diet treatment method were used for the toxicity evaluation against Microplites mediator adults. We tested 49 different pesticides (34 insecticides, 11 fungicides, 4 herbicides) at recommending concentration commonly used to control insect pests, disease and up-land weeds in chinese cabbage field. 16 insecticides, 11 fungicides, and 4 herbicides were shown to be low toxic to Microplites mediator adults in the treatment of body dipping.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.3
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• pp.186-192
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• 2009

PID controllers are simple in structure and easy for implementation. However, they may produce large overshoots and over-oscillatory responses. Combining PID control with other control techniques often results in advanced hybrid schemes that are able to improve pure PID controllers. This paper proposes hybrid controller for position control system of servo motor. The proposed controller is composed of a subcontroller and a parallel PID controller. The subcontroller improves the transient system performance while the PID controller is mainly responsible for the steady-state system performance. A very promising advantage of this hybrid scheme, in terms of controller synthesis, is that the subcontrollers and controller components can be designed separately. Systematic design methods for various controller components are developed. The proposed hybrid scheme is applied to a DC motor position servo system. The effectiveness of the proposed controller is verified through the computer simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.1
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• pp.13-21
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• 2005

This paper presents a fuzzy model-based approach for synchronization of time-delay chaotic system with input saturation. Time-delay chaotic drive and response system is respectively represented by Takagi-Sugeno (T-S) fuzzy model. Specially, the response system contains input saturation. Using the unidirectional linear error feedback and the parallel distributed compensation (PDC) scheme, we design fuzzy chaotic synchronization system and analyze local stability for synchronization error dynamics. Since time-delay in the transmission channel always exists, we also take it into consideration. The sufficient condition for the local stability of the fuzzy synchronization system with input saturation and time-delay is derived by applying Lyapunov-Krasovskii theory and solving linear matrix inequalities (LMI's) problem. A numerical example is given to demonstrate the validity of the proposed approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.71-78
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• 2002

A method of soft switching in the half bridge converter using a small saturable core is presented. For the soft switching, a small dead time of both switch off is made in a pair of MOSFET switch. The saturable core is of rectangular magnetization characteristics and the core flux swings from the minus to the plus saturation during ON time of the switch. The soft switching is realized in dead time by a resonance between the saturating inductance of the core and the stray capacitance of MOSFET. As an extension of this concept, instead of the saturable core, we propose a new soft switching circuit using a linear inductance and two switches, which is especially suitable for regulating the output and also for high frequency switching. A theoretical principle of soft switching presented here was confirmed by experiments on a half bridge converter of 1.25 KW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.90-98
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• 2013

The stereo system based on local matching is very popular due to its algorithmic simplicity, however it is limited to apply to various applications because it shows poor quality with low matching rates. In this paper, we propose and design a realtime stereo system based on an adaptive support-weight and the system shows low error rates and realtime performance. Generally, in the adaptive support-weight algorithm the intermediate computing results can not be reused to reduce the number of computations. In this research we modify the scheduling to reuse the intermediate results for the better performance by processing rows and columns separately. The nonlinear functions such as exponential or arc tangent have been designed with piecewise linear and step functions by empirical simulations and error analysis. The proposed architecture is composed of 9 processing elements for realtime performance. The proposed stereo system has been designed and synthesized using Donbu Hitek 0.18um standard cell library and can run up to 350Mhz operation frequency (33 frames per second) with 424K gates.

• Journal of IKEEE
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• v.24 no.1
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• pp.225-231
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• 2020

In this paper, we propose a method to accelerate BWN based on FPGA with limited resources for embedded system. Because of the limited number of logic elements available, a single computing unit capable of handling Conv-layer, FC-layer of various sizes must be designed and reused. Also, if the input feature map can not be parallel processed at one time, the output must be calculated by reading the inputs several times. Since the number of available BRAM modules is limited, the number of data bits in the BWN accelerator must be minimized. The image classification processing time of the BWN accelerator is superior when compared with a embedded CPU and is faster than a desktop PC and 50% slower than a GPU system. Since the BWN accelerator uses a slow clock of 50MHz, it can be seen that the BWN accelerator is advantageous in performance versus power.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.593-605
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• 2014

In this paper, we propose the efficient HW/SW co-design method of light-weight cryptography such as HIGHT, PRESENT and PRINTcipher using GEZEL. At first the symmetric cryptographic algorithms were designed using the GEZEL language which is efficiently used for HW/SW co-design. And for the improvement of performance the HW optimization theory such as unfolding, retiming and so forth were adapted to the cryptographic HW module conducted by FSMD. Also, the operation modes of those algorithms were implemented using C language in 8051 microprocessor, it can be compatible to various platforms. For providing reliable communication between HW/SW and preventing the time delay the improved handshake protocol was chosen for enhancing the performance of the connection between HW/SW. The improved protocol can process the communication-core and cryptography-core on the HW in parallel so that the messages can be transmitted to SW after HW operation and received from SW during encryption operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1441-1446
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• 2014

For the escape from a maze, the cooperative method by robot swarm was proposed in this paper. The robots can freely move by collecting essential data and making a decision in the use of sensors; however, a central control system is required to organize all robots for the escape from the maze. The robots explore new mazes and then send the information to the system for analyzing and mapping the escaping route. Three issues were considered as follows for the effective escape by multiple robots from the mazes in this paper. In the first, the mazes began to divide and secondly, dead-ends should be blocked. Finally, after the first arrivals at the destination, a shortcut should be provided for rapid escaping from the maze. The parallel-escape algorithms were applied to the different size of mazes, so that robot swarm can effectively get away the mazes.