• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.504-513
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• 2009

This paper proposes the new type LED driver modularization for illumination LED driver. The proposed LED driver circuit insulates a hot GND of AC input power and a cold GND of LED driver part by using a fly-back converter. In order to control easily the current of the LED, the fly-back converter is operated in the discontinuous mode with excellent dynamic characteristics, and the characteristics of the LED are verified after the closed loop control is performed using a KIA2431. The LED driver module allows the wide AC power input ranges and realizes the burst dimming function which directly regulates a PWM control IC. This paper describes the operation principle of the LED driver module and it is proved the usefulness through the real model with experimentation. Besides, this paper proposes the multi-channel LED driver which the miniaturized and modularized LED driver module are connected by parallel, and verified its propriety by experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.37-52
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• 2004

In this paper, Multistage Adaptive Partial PIC eliminating effectively the multiple access and multipath interference for DS-CDMA based W-CDMA uplink system is designed and its performance is evaluated with computer simulation. By adaptively controlling the slope of the soft limiter with received signals, the efficiency of the soft limiter can be maximized and the better performance is obtained by solving error floor problem using further precise generation of interference signal. As a result, The proposed Multistage Adaptive Partial PIC with simple optimizing method for time-variant channel showed optimum performance at fewer stages. Besides fewer stages, the interference cancellation at the output of the rake receiver considerably reduced system complexity. The Multistage Adaptive Partial PIC with precise generation and efficient cancellation of interference signal can solve error eoor problem, resulted from initial false detection and improve system performance of high data rate system.

• Journal of the Korea Computer Graphics Society
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• v.24 no.2
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• pp.11-20
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• 2018

We propose a new method particle-based method that explicitly preserves thin liquid sheets for animating liquids on CPU-GPU heterogeneous computing framework. Our primary contribution is a particle-based framework that splits at thin points and collapses at dense points to prevent the breakup of liquid on GPU. In contrast to existing surface tracking methods, the our method does not suffer from numerical diffusion or tangles, and robustly handles topology changes on CPU-GPU framework. The thin features are detected by examining stretches of distributions of neighboring particles by performing PCA(Principle component analysis), which is used to reconstruct thin surfaces with anisotropic kernels. The efficiency of the candidate position extraction process to calculate the position of the fluid particle was rapidly improved based on the CPU-GPU heterogeneous computing techniques. Proposed algorithm is intuitively implemented, easy to parallelize and capable of producing quickly detailed thin liquid animations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.5
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• pp.1-7
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• 2009

When constructing various mobile networks including sensor networks, the problem of finding the layout or graph to interconnect the terminals or nodes of the network may come up. Providing a common scheme that can be applied to the kind of problems, and formulating the bounds of the run time and the result of the algorithm from the scheme, one may evaluate precisely the plan of constructing analogous network systems. This paper, dealing with EMST(Euclidean Minimum Spanning Tree) that represents such problems, provides the scheme for constructing EMST by parallel processing over distributed environments, and the ground for determining the maximum difference of the layout or the graph produced from the scheme: the difference from EMST. In addition, it provides the upper bound of the run time of the algorithm from the scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.3
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• pp.31-37
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• 2012

This paper presents an efficient hardware architecture to enable the high-speed Givens rotation-based QR decomposition. The proposed architecture achieves a highly parallel givens rotation process by maximizing the number of pivots selected for parallel zero-insertions. Sign-select lookahed (SSL)-CORDIC is also efficiently used for the high-speed givens rotation. The performance of QR decomposition hardware considerably increases compared to the conventional triangular systolic array (TSA) architecture. Moreover, the circuit area of QR decomposition hardware was reduced by decreasing the number of flip-flops for holding the pre-computed results during the decomposition process. The proposed QR decomposition hardware was implemented using TSMC $0.25{\mu}m$ technology. The experimental results show that the proposed architecture achieves up to 70 % speed-up over the TACR/TSA-based architecture for the $8{\times}8$ matrix decomposition.

• Journal of IKEEE
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• v.23 no.4
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• pp.1314-1320
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• 2019

In this paper, we propose a new method for optimizing bit operations and applying them to DNN(Deep Neural Network) in software environment. As a method for this, we propose a packing function for bitwise optimization and a masking matrix multiplication operation for application to DNN. The packing function converts 32-bit real value to 2-bit quantization value through threshold comparison operation. When this sequence is over, four 32-bit real values are changed to one 8-bit value. The masking matrix multiplication operation consists of a special operation for multiplying the packed weight value with the normal input value. And each operation was then processed in parallel using a GPU accelerator. As a result of this experiment, memory saved about 16 times than 32-bit DNN Model. Nevertheless, the accuracy was within 1%, similar to the 32-bit model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of IKEEE
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• v.24 no.2
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• pp.392-402
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• 2020

This paper proposes a solar tracking system without photo-sensors. The system can be classified into four modules: Solar Tracking, MPPT, ESS, and Real-Time Monitoring. Nine solar panels, as a basic unit, are adopted with grid structures of different heights to reduce wind influence and to enable solar tracking without photo-sensors. The low-cost MCU implements MPPT method which generates PWM switching signal for boost converter. The unit of ESS consists of three-series and four-parallel lithium-ion batteries in order to enable monitoring for abnormalities in temperature and electrical characteristics of battery. Four MCUs used in the system consists of two AVR Atmega128, and two Raspberry PI, and they exchanges operation informations. Experimental results of the proposed system show the solar tracking performance, the possibility of on-site and remote monitoring and the convenience of maintenance based on IoT technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.