• Journal of Bio-Environment Control
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• v.22 no.4
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• pp.316-321
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• 2013

This study was carried out to analyze heat transfer characteristics and heat flow through air-inflated double layer PO film with thermal resistance method. The experiments was conducted in the laboratory controlled air temperature between 258.0 K and 278.0 K. The experimental materials were made up two layers PO film and an inflated-air layer. The thickness of air-inflated layer was fixed at 3 types of 110, 175, 225 mm. The electrical circuit analogy for heat transfer by conduction, radiation and convection was introduced. Experimental data shows that the dominant thermal resistance in heat transfer through the air-inflated double layer film was convection. Calculation errors were 1.1~18.5 W for heat flow. In result, the method of thermal resistance could be introduced for analysis of heat flow characteristics through air-inflated double layer film.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.27-34
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• 2004

The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.257-259
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• 2019

본 논문은 광물 탐사를 위한 25kW급 양극성 펄스전원장치에 대해 기술한다. 소프트스위칭 기반의 고효율 LCC 공진형 컨버터와 풀 브리지 기반 양극성 펄스 스위칭부로 구성된 단위 모듈(500V, 12.5A)을 기반으로 설계한다. LCC 공진형 컨버터는 전류의 rms값을 줄이기 위해 공진 전류모양을 사다리꼴 형태로 설계하여 도전 손실측면에서 크게 개선되었고, 높은 전력밀도를 달성하기 위해 변압기의 누설 인덕턴스를 공진 파라메터로 활용한다. 추가적으로, 짧은 펄스폭을 가지도록 설계된 게이트 구동 회로는 출력을 DC에서 8kHz의 넓은 주파수 범위에서 동작시킬 뿐만 아니라 게이트 신호를 전달하기 위한 변압기의 사이즈를 줄이기 위해 제안된다. 단위모듈 형태로 개발된 양극성 펄스전원장치는 4개의 모듈이 직병렬로 결선되어 부하조건에 따라 Grounded dipole mode (2kV, 12.5A) 또는 Loop mode (500V, 50A)로 동작한다. 4모듈 직병렬 운전 시 발생하는 모듈 간 전압 불균형 문제를 해결하기 위해 메인 변압기에 보상권선이 감긴다. 본 논문에서는 개발된 양극성 펄스전원 장치의 설계를 저항부하 실험 및 태백산 탐사시험 결과를 바탕으로 검증한다.

• Journal of Advanced Navigation Technology
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• v.23 no.4
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• pp.309-315
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• 2019

This paper proposes an implementation of unequal power divider with 1:3 and 1:4 splitting ratio in multi-section structure using CPW and offset coupled transmission line. The power divider consists of a multi-section transmission line and a circuit with parallel capacitors and resistors. A multi-section transmission line was implemented by decomposing a ${\lambda}/4$ single transmission line terminated by an arbitrary impedance and converging it with a multi-section transmission line shorter than $90^{\circ}$ electrical length, and RC parallel circuits were connected between transmission lines to obtain reflection coefficient of output port and isolation characteristics between the output port. In this way, it was confirmed that the transmission lines at the unequal power divider designed at 2 GHz were shorter than ${\lambda}/4$ and implemented at least 27% less than the conventional ones, and that the broadband characteristics could be obtained.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1045-1046
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• 2006

최근 반도체 및 FPD 산업에서 Glass의 사이즈, 무게의 증가함에 따라 물류 이송 장비의 전원장치인 비접촉 전원장치의 크기와 용량이 증가하는 추세이며, 또한, 클린룸의 규모가 커짐에 따라 물류 이송 장비 시스템의 길이가 길어지고 Vehicle의 수가 증가하는 추세이다. 본 논문에서는 여러 대의 Vehicle간 독립제어가 가능하고, 물류 이송 장비의 구조가 직선부분과 곡선부분이 혼용되어진 구조에서도 사용 가능한 정전류 비접촉 전원장치의 주요 전력변환 토플로지 별 해로해석, 제어방법을 제시하였고 특히 직 병렬 공진 컨버터의 회로해석, 특성평가를 행하였다. 이 특성평가를 바탕으로 정전류 비접촉 전원장치의 시제품을 제작하여 저항성 부하와 선형 구동 시스템에 적용한 Vehicle 2대를 부하로 사용하여 실험을 행하여 실제 적용, 가능함을 보이고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1686-1696
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• 2022

The impedance matching circuit design technique based on the phasor plot introduced in this paper is based on the impedance triangle of electric circuit. It is a technique that designs through the construction of a phasor figure using the values given to the matching circuit design. The design pattern is based on L-type, inverted L-type, T-type, and 𝜋-type, and unknown reactance elements are determined through phasor shapes. In this paper, using a design by phasor plot, we design several cases, such as the case where the input and output ports are pure resistance and have reactance. It was confirmed that the design value was verified by serial-parallel equivalent conversion to achieve matching. This design technique can immediately grasp the phase or size of input/output power, so it is expected to be applied mainly in a low frequency band due to rapid design change and application.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.59-68
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• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.620-626
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• 2015

In this paper, a 2~6 GHz wideband GaN power amplifier MMIC is designed and fabricated using a second-order all-pass filter for input impedance matching and an LC parallel resonant circuit for minimizing an output reactance component of the transistor. The second-order all-pass filter used for wideband lossy matching is modified in an asymmetric configuration to compensate the effect of channel resistance of the GaN transistor. The power amplifier MMIC chip that is fabricated using a $0.25{\mu}m$ GaN HEMT foundry process of Win Semiconductors, Corp. is $2.6mm{\times}1.3mm$ and shows a flat linear gain of about 13 dB and input return loss of larger than 10 dB. Under a saturated power mode, it also shows output power of 38.6~39.8 dBm and a power-added efficiency of 31.3~43.4 % in 2 to 6 GHz.