• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• Journal of IKEEE
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• v.16 no.2
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• pp.102-108
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• 2012

3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

• Transactions of the Society of Information Storage Systems
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• v.3 no.4
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• pp.183-190
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• 2007

In most hard disk drives that apply the ramp load/unload technology, the head is unloaded at the outer edge of the disk while the disk is rotating. During the unloading process, slider-disk contacts may occur by lift-off force and rebound of the slider. The main issue of this paper is to prevent the slider-disk contact by rebound, and we apply a disk bump to the unloading process. To do so, first, the ranges of bump dimension are determined. Second, the stability of each bump is checked by dynamic simulation. Finally, unload simulations are performed for stable bump designs. As a result of these steps, the effect of the bump design and the position for the unloading performance were investigated. As a consequence, we propose the optimal bump design to improve the unloading performance. Furthermore, we can identify to remove rebound contact by applying a bump on disk during the unloading process.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.9-14
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• 2012

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.833-836
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• 2007

Load/Unload technology has more benefits than the conventional CSS technology. However, it remains unsolved technical problem on the unloading process. While the slider climbs up the ramp at the outer edge of the disk, the possibility of the slider-disk contact by lift-off force and rebound of the slider increases. This paper focuses on no slider-disk contact. To prevent the slider-disk contact, we apply the disk bump on disk outer edge proceeding unload. Firstly, in the simulation, the bump dimension is determined by changing bump design parameters. Secondly, dynamic stability of slider have to be checked on disk bump before unload analysis, and unload analysis is performed by applying stable bump shapes to unload simulation. Thirdly, we select optimal bump shape to improve unload performance by unload analysis. Finally, in the experiment, the disk bump is mechanically manufactured by pressing disk surface using diamond tip. That is variously processed by changing pressing pressure. After confirming bump shape by nano-scanner, proper bump shape is applied to real experimental unload process. Through this investigation, we propose the optimal bump design to prevent the slider-disk contact, and then we can realize improved unloading performance.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.9-11
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• 1999

3차원 그래픽 랜더링 파이프라인(3D Graphics Rendering Pipeline)은 크게 지오메트리 프로세싱(Geometry Processing)과 레스터라이제이션(Rasterization)으로 구성되어 있다. 본 논문에서는 래스터라이저와 프레임버퍼사이의 대역폭으로 인한 병목점을 분석하고, 그 한계를 극복해 낼 수 있도록 프로세서 메모리 집적구조를 이용하여 랜더링 시스템을 설계, 성능 분석한다. 프레임버퍼의 집적으로 인한 메모리 대역폭을 이용하기 위해, 각 픽셀 처리에 필요한 로직을 포함하는 SIMD 타입의 픽셀 처리 프로세서가 메모리 어레이와 밀결합(tightly coupled)된다. 제안하는 구조는 래스터라이저 로직과 프레임 버퍼가 단일 칩으로 구성되었고, 텍스쳐 매핑, 범프 매핑, 안티알리아싱, 깊이 버퍼를 지원하며 초당 5백만 이상의 삼각형을 처리할 수 있는 고성능 랜더링 시스템이다.

• 유체기계공업학회:학술대회논문집
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• 2001.11a
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• pp.129-134
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• 2001

The paper presents the optimal design of a oil-free two-stage compressor, which is driven by 75 kW motor at an operating speed of 39,000 rpm, and the pressure ratio of which is up to 4. First, an attempt is made to obtain the optimal design of a bump bearing which supports a compressor rotor. Second, bump bearings and shaft are considered simultaneously, and the weighted sum of rotor weight and frictional torque is minimized. Finally, the optimal geometry of compressor wheel is considered. The mean efficiency and the - minimum efficiency are maximized respectively. The results presented in this paper provide important design information necessary to reduce the energy loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.307-320
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• 1989

This paper presetns new design of the Modified Chemical Vapor Deposition(MCVD) system for optical fiber preform fabrication. It contains a glass working lathe, raw material supplier and exhaust gas treatment apparatus as fundamental instruments for MCVD process, graded index fiber design, characteristic of process and the experimenta arrangement to measure the refractive index profile of MCVD preforms, respectively. From the investigation results, it is shown that an ideal graded index fiber preform does not exhibit a center dip or bump.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.11a
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• pp.185-188
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• 2006

생체 신경세포를 모방하는 진동성 신경 셀을 아날로그 집적회로로 설계한다. 진동성 신경셀은 입력신호 취합을 위한 취합회로와 신경 펄스 발생회로, 신경펄스 발생을 위한 범프회로와 트랜스콘덕터로 이루어지는 부성저항 블록으로 구성된다. $0.35{\mu}m$ 2중 폴리 공정 파라미터를 이용하여 SPICE 모의실험을 실시하여 입력 신호 유무 및 크기변화에 따른 출력 펄스의 발생을 얻어 진동성 신경회로의 가능성을 확인한다.