• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.91-102
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• 2005

Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.7
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• pp.916-922
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• 2014

Diode rectifiers have been widely used for an AC to DC converter. But a big problem is that they include large harmonics components in the input currents. A 12-pulse configuration with phase shifting transformer is useful for reducing them. however, it still includes the ($12{\pm}1$)th (m; integer) harmonics in the input currents. In this paper, we propose a single-phase square wave auxiliary voltage supply which is inserted in the middle DC bus. It reduces harmonics especially the 11th and 13th and the harmonic characteristic becomes almost equivalent to a 24-pulse rectifier. Theoretical analysis of the combined 12-pulse diode rectifier with the auxiliary supply is presented and a control method of the auxiliary supply is proposed. The reduction in the input current harmonics is verified by simulation using software PSIM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.140-150
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• 2006

In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6B
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• pp.527-533
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• 2006

In this paper, we analyze the performance of MAC (Media Access Control) layer in DSRC (Dedicated Short Range Communication). It will be widely applied for ITS (Intelligent Transportation System) services; for example ETC (Electric Toll Control), BIS (Bus Information System) etc., needed to small packet size. But If ITS service is evolving to advance ITS, ADIS (Advanced Driver Information Systems) and AVHS (Advanced Vehicle Highway System) etc, be needed larger packet size. In the future, it may offer more various services such as traffic information, collection, and multimedia information. There are two kind of physical media, IR(Infrared) and RF(Radio frequency). And each system has their own protocol that is adaptive in special characteristics of physical medium for using efficiently limited radio resources. In this paper, we analyze the special characteristics of each system. And we study practical use of some related services expected to be used in the near future, by analyzing the transmission efficiency in each DSRC system.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.152-159
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• 2004

The Grid system is an emerging computing infrastructure that will substitute for existing distributed systems. However end users have a difficulty in using the Grid because of its complicated usage, which is an inherent characteristic from the heterogeneous mechanism of the Grid. In this paper, we present the JCML(Job Control Markup Language) and its GUI-based editor, which not only provide users with ease of use, improved working environment, but assist users to execute their jobs efficiently The JCML is a job control language that improves the RSL of Globus, which defines global services in Grid. The JCML is designed to support flexibility among various Grid services using standard XML. And it makes use of a graph representation method, GXL(Graph eXchange Language), to specify detailed job properties and dependencies among jobs using nodes and edges. The JCML editor provides users with GUI-based interface. With the JCML editor, a complicated job order can be easily completed using very simple manipulations with a mouse, such as a drag-and-drop.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• Journal of Korean Society of Transportation
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• v.34 no.1
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• pp.81-94
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• 2016

The Korean real-time traffic responsive control systems, Cycle Offset Split Model of Seoul (COSMOS), employs a single theoretical model to estimate the degree-of-saturation (DS) on approaches. However, the deployment of the system has been accomplished without practical consideration of its field performance. This paper delivers a diagnosis study performed to find the relationships yet known on the DS values against the operational conditions unproved in theory but ordinarily observed in field practice. Based on the analysis of the historical log data (476,505 cycles) obtained from the COSMOS server, it was found; (1) full coverage of lane detections should perform better than the sample coverage of detection in ordinary conditions, (2) the sample coverage of detection perform better than the other case with an exclusive bus lane, (3) detection in which a shared lane is involved provide poor estimation of DS, (4) poor DS estimation when a detection lane is adjacent to a shared lane, and (5) the DS values obtained during a day can hardly be stable all time. The findings suggest traffic engineers a progressive direction to move forward for the next real-time traffic control systems.

• Journal of the Korean Society of Marine Environment & Safety
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• v.21 no.6
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• pp.759-769
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• 2015

Diode rectifiers are very popular in industry. However, they include large low-order harmonics in the input current and do not satisfy harmonic current content restrictions. To reduce the harmonics to the power system, several methods have been introduced. It is heavy and expensive solution to use passive filters as the solution for high power application. Another solution for the harmonic filter is utilization of active filter, but it is too expensive solution. Diode rectifiers with configurations using switching device have been introduced, but they are very complicated. The combined 12-pulse diode rectifier with the square auxiliary voltage supply has been introduced. It has the advantages that auxiliary circuit is simple and inexpensive compared to other strategies. The advanced auxiliary voltage supply in this thesis is presented as a new solution. When the square auxiliary voltage supply applied, the improvement of THD is 6~60[%] in whole load range. But when the advanced auxiliary voltage supply applied, it shows stable and excellent reduction effect of THD as 57~71[%]. Especially, for the case with 10[%] load factor, reduction effect of THD has little effect as 6[%] in the case of inserting a square auxiliary voltage supply. But when the proposed new solution applied, reduction effect has excellent effect as 71[%]. Theoretical analysis of the combined 12-pulse diode rectifier with the advanced auxiliary voltage supply is presented and control methods of the auxiliary supply is proposed. The reduction in the input current harmonics is verified by simulation using software PSIM.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.