• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.769-771
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• 2005

유비쿼터스 컴퓨팅의 기반 설비인 센서 네트워크는 많은 수의 센서 노드들로 구성되며, 각 센서 노드의 하드웨어는 매우 작은 규모이다. 또한 최소한의 전력 소모를 위하여 센서 노드들은 동적으로 재구성되며, 노드들 간의 통신은 무선 네트워크를 통하여 이루어진다. 센서 네트워크는 구축 목적에 따라 네트워크 토폴로지 및 라우팅 방식이 결정되어야 하고, 이와 더불어 센서 노드의 하드웨어와 소프트웨어도 필요에 따라 다양하게 변경되어야 한다. 따라서 센서 네트워즈가 구현되기 전에 시스템 동작과 성능을 예측할 수 있고 소프트웨어 개발 환경도 제공해주는 시뮬레이터가 사용 가능하다면, 시스템 개발 기간을 크게 단축시킬 수 있을 것이다. 기존의 센서 네트워크 시뮬레이터들은 특별한 응용을 위한 특정 기반의 하드웨어와 운영체제에 국한되어 개발되었기 때문에 다양한 센서 네트워크 환경을 지원하기에는 한계가 있으며, 센서 네트워크 설계상의 주요 요소인 전력 소모량 분석이 포함되지 않았다. 따라서 본 연구에서는 특정한 응용이나 운영체제에 제한을 받지 않으면서 다양하게 센서 네트워크 환경을 설계 및 검증할 수 있고 전력 소모량 추정도 가능한 시뮬레이터를 개발하는 것을 목표로 하였다. 본 연구에서 개발한 시뮬레이터는 기계명령어-레일(machine instruction-level)의 이산-사건 시뮬레이션(discrete-event simulation) 기법을 이용함으로써 실제 센서 노드의 프로그램 실행 및 관련 동작들을 세부적으로 예측하는 데 사용될 수 있도록 하였다. 시뮬레이션의 작업부하(Workload)인 명령어 트레이스(instruction trace)로는 ATmega128L 마이크로컨트롤러용으로 크로스 컴파일된 인텔 헥스-레코드 형식(.hex) 또는 S-레코드 형식(.srec)의 파일을 사용한다.들을 해결하고자 프라이버시보호에 새로운 키 생성 방법을 통한 강력한 프로토콜을 제안 한다.하였으나 사료효율은 증진시켰으며, 후자(사양, 사료)와의 상호작용은 나타나지 않았다. 이상의 결과는 거세비육돈에서 1) androgen과 estrogen은 공히 자발적인 사료섭취와 등지방 침적을 억제하고 IGF-I 분비를 증가시키며, 2) 성선스테로이드호르몬의 이 같은 성장에 미치는 효과의 일부는 IGF-I을 통해 매개될 수도 있을을 시사한다. 약 $70 {\~} 90\%$의 phenoxyethanol이 유상에 존재하였다. 또한, 미생물에 대한 항균력도 phenoxyethanol이 수상에 많이 존재할수록 증가하는 경향을 나타내었다. 따라서, 제형 내 oil tomposition을 변화시킴으로써 phenoxyethanol의 사용량을 줄일 수 있을 뿐만 아니라, 피부 투과를 감소시켜 보다 피부 자극이 적은 저자극 방부시스템 개발이 가능하리라 보여 진다. 첨가하여 제조한 curd yoghurt는 저장성과 관능적인 면에서 우수한 상품적 가치가 인정되는 새로운 기능성 신제품의 개발에 기여할 수 있을 것으로 사료되었다. 여자의 경우 0.8이상이 되어서 심혈관계 질환의 위험 범위에 속하는 수준이었다. 삼두근의 두겹 두께는 남녀 각각 $20.2\pm8.58cm,\;22.2\pm4.40mm$으로 남녀간에 유의한 차이는 없었다. 조사대상자의 식습관 상태는 전체 대상자의 $84.4\%$가 대부분이 하루 세끼 식사를 규칙적으로 하고 있었으며 식사속도는 허겁지겁 빨리 섭취하는 경우가 남자는 $31.0\%$, 여자는 $21.4\%$로 나타났고 이들을 제외한 나머지 사람들은 보통 속도 혹은 충분한 시간을 가지고 식사를 하였

• The Journal of the Korea Contents Association
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• v.19 no.2
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• pp.469-476
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• 2019

Robotic motion is designed by the rotation and the translation of multiple joint coordinates in a three-dimensional space. Joint coordinates are generally modeled by homogeneous transform matrix. However, the complexity of three dimensional motions prefers the visualization methods based on simulation environments in which models and generated motions work properly. Many simulation environments have the limitations of usability and functional extension from platform dependency and interpretation of predefined commands. This paper proposes the web-based three dimensional simulation environment toward high user accessibility. Also, it covers the small size web server that is linked with Python script. The non linearities of robot control apply to verify the computing efficiency, the process management, and the extendability of user scripts.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.2164-2178
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• 1998

본 논문에서는 한 사이클에 여러 개의 명령들이 다중 이슈되어 명령어 수준에서 병렬처리되는 ILP 프로세서의 성능을 측정하고 평가하는 시스템을 개발한다. 개발되는 시스템은 C 컴파일러와 시뮬레이터로 구성된다. C 컴파일러는 C 소스 프로그램을 입력으로 받아 3-주소 코드형태의 중간언어를 생성한다. 생성된 중간언어는 ILP 프로세서의 환경 파라미터와 함께 시뮬레이터에 입력되어 시뮬레이션된 후 메모리 내용, 수행된 클럭 수 및 명령 트레이스, 수행된 명령들의 동적 빈도수, 분기명령의 예측률, profiling 정보 등을 생성한다. 개발된 성능측정 시스템의 동작 검증을 위하여 순차이슈 되어 정적으로 스케쥴링 되는 조건실행 방식의 성능과 분기처리 방식의 성능을 측정하여 분석한다.

• Communications of Mathematical Education
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• v.29 no.4
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• pp.573-588
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• 2015

In this paper, we introduce development process and application of a simple and effective model of a statistics laboratory using open source software R, one of leading language and environment for statistical computing and graphics. This model consists of HTML files, including Sage cells, video lectures and enough internet resources. Users do not have to install statistical softwares to run their code. Clicking 'evaluate' button in the web page displays the result that is calculated through cloud-computing environment. Hence, with any type of mobile equipment and internet, learners can freely practice statistical concepts and theorems via various examples with sample R (or Sage) codes which were given, while instructors can easily design and modify it for his/her lectures, only gathering many existing resources and editing HTML file. This will be a resonable model of laboratory for studying statistics. This model with bunch of provided materials will reduce the time and effort needed for R-beginners to be acquainted with and understand R language and also stimulate beginners' interest in statistics. We introduce this interactive statistical laboratory as an useful model for beginners to learn basic statistical concepts and R.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.4
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• pp.685-692
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• 2024

In this paper, we propose a new CNN model to improve the recognition performance of command voice signals. This method obtains a spectrogram image after performing a short-time Fourier transform (STFT) of the input signal and improves command recognition performance through supervised learning using a CNN model. After Fourier transforming the input signal for each short-time section, a spectrogram image is obtained and multi-classification learning is performed using a CNN deep learning model. This effectively classifies commands by converting the time domain voice signal to the frequency domain to express the characteristics well and performing deep learning training using the spectrogram image for the conversion parameters. To verify the performance of the speech recognition system proposed in this study, a simulation program using Tensorflow and Keras libraries was created and a simulation experiment was performed. As a result of the experiment, it was confirmed that an accuracy of 92.5% could be obtained using the proposed deep learning algorithm.

• KIISE Transactions on Computing Practices
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• v.23 no.9
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• pp.564-571
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• 2017

The burst loading of a pre-created cache-image is an effective method to reduce the instruction cache misses in the early stage of the program execution. It is useful to alleviate the performance degradation as well as the energy inefficiency, which is induced by the concentrated cold misses at the instruction cache. However, there are some defects, including software overhead on the compiler and installer. Furthermore, there are several mismatches as a result of the dynamic properties for specific applications. This paper addresses these issues and proposes a cache-image maintenance/recreation policy that can conduct dynamic management using a hardware-assisted method. The results of the simulation show that the proposed method can maintain the cache-image with a proper size and validity.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.39-49
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• 2006

This paper proposes an efficient verification environment of PCI Express controller that is the future I/O interface. This verification environment consists of a test vector generator, a test bench, and two abstract memories. We also define the assembler set to generate the verification scenarios. In this paper, we propose the random test environment which consists of a random vector generator, a .simulator part, and a compare engine. This verification methodology is useful to find the special errors which are not detected by the basic-behavioral test and hardware-design test.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1252-1262
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• 1988

This paper describes a functional-level design and simulation of Graphics Processor(GP) which can be used in various graphics systems. GP is divided into two parts: One is CPU, and the other is the interface to I/O peripherals. In order to achieve fast execution of graphics instructions, the CPU has special ALU, barrel shifter and window comparator and a FIFO for instruction prefetch. I/O part controls the DRAM and VRAM which constitute the GP's local memory, generates the signals to drive monitor, and communicates with the host processor. The functional simulation of CPU was done on Daisy workstation while the I/O part was designed using GENESIL, a silicon compiler.

• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.