• Title/Summary/Keyword: 메모리 효율

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A Public-key Cryptography Processor supporting P-224 ECC and 2048-bit RSA (P-224 ECC와 2048-비트 RSA를 지원하는 공개키 암호 프로세서)

  • Sung, Byung-Yoon;Lee, Sang-Hyun;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.522-531
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    • 2018
  • A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

A Method of Adaptive ISF Split Vector Quantization Using Normalized Codebook (정규화 코드북을 이용한 분할 벡터 구조의 ISF 적응적 양자화 기법)

  • Piao, Zhigang;Lim, Jong-Ha;Hong, Gi-Bong;Lee, In-Sung
    • The Journal of the Acoustical Society of Korea
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    • v.30 no.5
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    • pp.265-272
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    • 2011
  • In most of the ISF (or LSF) based real time speech codec, SVQ (split vector quantization) method is used to decrease the quantizer complexity and memory size of codebook. However, it produces drawback that the level of correlation between code vectors can not be used during vector splits. This paper presents a new method of adaptive ISF vector quantization, which compensates the drawbacks of SVQ structured quantizer for wideband speech codec. In each different frame, the proposed method makes use of the correlation between splitted vectors by adaptively changing codebook distribution according to ordering property of ISF. The algorithm is evaluated in AMR-WB, and shows about 1.5 bit per frame improvement.

Consensus-based Autonomous Search Algorithm Applied for Swarm of UAVs (군집 무인기 활용을 위한 합의 기반 자율 탐색 알고리즘)

  • Park, Kuk-Kwon;Kwon, Ho-Jun;Choi, Eunju;Ryoo, Chang-Kyung
    • Journal of Advanced Navigation Technology
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    • v.21 no.5
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    • pp.443-449
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    • 2017
  • Swarm of low-cost UAVs for search mission has benefit in the sense of rapid search compared to use of single high-end UAV. As the number of UAVs forming swarm increases, not only the time for the mission planning increases, but also the system to operate UAVs has excessive burden. This paper addresses a decentralized area search algorithm adequate for multiple UAVs which takes advantages of flexibility, robustness, and simplicity. To down the cost, it is assumed that each UAV has limited ability: close-communication, basic calculation, and limited memory. In close-communication, heath conditions and search information are shared. And collision avoidance and consensus of next search direction are then done. To increase weight on un-searched area and to provide overlapped search, the score function is introduced. Performance and operational characteristics of the proposed search algorithm and mission planning logic are verified via numerical simulations.

An Implementation of Embedded SIP User Agent under Wireless LAN Area (Wireless LAN 환경에서 임베디드 SIP User Agent 구현)

  • Park Seung-Hwan;Lee Jae-Heung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.3
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    • pp.493-497
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    • 2005
  • This paper is about the research of the User Agent implementation under wireless embedded environment, using SIP which is one of protocol components construct the VoIP system. The User Agent is made of the User Agent configuration block, the device thread block to control devices and the SIP stack block to process SIP messages. The device thread consists of the RTP thread and the sound lard device processing block. Futhermore, the SIP stack consist of the worker thread to process proxy events, the SIP transceiver and SIP thread to transfer and receive SIP messages. The H/W platform is a board included the Intel's XScale PXA255 processor, flash memory, SDRAM, Audio CODEC module and wireless LAN threough PCMCIA socket, furthermore a microphone and headphone is used by the audio 1/0. The system has embedded linux kernel 2.4.19. For embedded environment, the function of User Agent and SIP method is diminished. Finally, the resource of system could be reduced about $12.9\%$, compared to overall system resource, by minimizing peripherals control and excepting TCP.

V-NAND Flash Memory 제조를 위한 PECVD 박막 두께 가상 계측 알고리즘

  • Jang, Dong-Beom;Yu, Hyeon-Seong;Hong, Sang-Jin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.236.2-236.2
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    • 2014
  • 세계 반도체 시장은 컴퓨터 기능이 더해진 모바일 기기의 수요가 증가함에 따라 메모리반도체의 시장규모가 최근 빠른 속도로 증가했다. 특히 모바일 기기에서 저장장치 역할을 하는 비휘발성 반도체인 NAND Flash Memory는 스마트폰 및 태블릿PC 등 휴대용 기기의 수요 증가, SSD (Solid State Drive)를 탑재한 PC의 수요 확대, 서버용 SSD시장의 활성화 등으로 연평균 18.9%의 성장을 보이고 있다. 이러한 경제적인 배경 속에서 NAND Flash 미세공정 기술의 마지막 단계로 여겨지는 1Xnm 공정이 개발되었다. 그러나 1Xnm Flash Memory의 생산은 새로운 제조설비 구축과 차세대 공정 기술의 적용으로 제조비용이 상승하는 단점이 있다. 이에 따라 제조공정기술을 미세화하지 않고 기존의 수평적 셀구조에서 수직적 셀구조로 설계 구조를 다양화하는 기술이 대두되고 있는데 이 중 Flash Memory의 대용량화와 수명 향상을 동시에 추구할 수 있는 3D NAND 기술이 주목을 받게 되면서 공정기술의 변화도 함께 대두되고 있다. 3D NAND 기술은 기존라인에서 전환하는데 드는 비용이 크지 않으며, 노광장비의 중요도가 축소되는 반면, 증착(Chemical Vapor Deposition) 및 식각공정(Etching)의 기술적 난이도와 스텝수가 증가한다. 이 중 V-NAND 3D 기술에서 사용하는 박막증착 공정의 경우 산화막과 질화막을 번갈아 증착하여 30layer 이상을 하나의 챔버 내에서 연속으로 증착한다. 다층막 증착 공정이 비정상적으로 진행되었을 경우, V-NAND Flash Memory를 제조하기 위한 후속공정에 영향을 미쳐 웨이퍼를 폐기해야 하는 손실을 초래할 수 있다. 본 연구에서는 V-NAND 다층막 증착공정 중에 다층막의 두께를 가상 계측하는 알고리즘을 개발하고자 하였다. 증착공정이 진행될수록 박막의 두께는 증가하여 커패시터 관점에서 변화가 생겨 RF 신호의 진폭과 위상의 변화가 생긴다는 점을 착안하여 증착 공정 중 PECVD 장비 RF matcher와 heater에서 RF 신호의 진폭과 위상을 실시간으로 측정하여 데이터를 수집하고, 박막의 두께와의 상관성을 분석하였다. 이 연구 결과를 토대로 V-NAND Flash memory 제조 품질향상 및 웨이퍼 손실 최소화를 실현하여 제조 시스템을 효율적으로 운영할 수 있는 효과를 기대할 수 있다.

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High Speed Implementation of LEA on ARMv8 (ARMv8 상에서 LEA 암호화 고속 구현)

  • Seo, Hwa-jeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.10
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    • pp.1929-1934
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    • 2017
  • Lightweight block cipher (Lightweight Encryption Algorithm, LEA), is the most promising block cipher algorithm due to its efficient implementation feature and high security level. The LEA block cipher is widely used in real-field applications and there are many efforts to enhance the performance of LEA in terms of execution timing to achieve the high availability under any circumstances. In this paper, we enhance the performance of LEA block cipher, particularly on ARMv8 processors. The LEA implementation is optimized by using new SIMD instructions namely NEON engine and 24 LEA encryption operations are simultaneously performed in parallel way. In order to reduce the number of memory access, we utilized the all NEON registers to retain the intermediate results. Finally, we evaluated the performance of the LEA implementation, and the proposed implementations on Apple A7 and Apple A9 achieved the 2.4 cycles/byte and 2.2 cycles/byte, respectively.

A Study on Frequency Hopping Signal Detection Using a Polyphase DFT Filterbank (다상 DFT 필터뱅크를 이용한 도약신호 검출에 관한 연구)

  • Kwon, Jeong-A;Lee, Cho-Ho;Jeong, Eui-Rim
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.4
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    • pp.789-796
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    • 2013
  • It is known that the detection of hopping signals without any information about hopping duration and hopping frequency is rather difficult. This paper considers the blind detection of hopping signal's information such as hopping duration and hopping frequency from the sampled wideband signals. In order to find hopping information from the wideband signals, multiple narrow-band filters are required in general, which leads to huge implementation complexity. Instead, this paper employs the polyphase DFT(discrete Fourier transform) filterbank to reduce the implementation complexity. This paper propose hopping signal detection algorithm from the polyphase DFT filterbank output. Specifically, based on the binary image processing, the proposed algorithm is developed to decrease the memory size and H/W complexity. The performance of the proposed algorithm is evaluated through the computer simulation and FPGA (field programmable gate array) implementation.

Modified TDS (Task Duplicated based Scheduling) Scheme Optimizing Task Execution Time (태스크 실행 시간을 최적화한 개선된 태스크 중복 스케줄 기법)

  • Jang, Sei-Ie;Kim, Sung-Chun
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.6
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    • pp.549-557
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    • 2000
  • Distributed Memory Machine(DMM) is necessary for the effective computation of the data which is complicated and very large. Task scheduling is a method that reduces the communication time among tasks to reduce the total execution time of application program and is very important for the improvement of DMM. Task Duplicated based Scheduling(TDS) method improves execution time by reducing communication time of tasks. It uses clustering method which schedules tasks of the large communication time on the same processor. But there is a problem that cannot optimize communication time between task sending data and task receiving data. Hence, this paper proposes a new method which solves the above problem in TDS. Modified Task Duplicated based Scheduling(MTDS) method which can approximately optimize the communication time between task sending data and task receiving data by checking the optimal condition, resulted in the minimization of task execution time by reducing the communication time among tasks. Also system modeling shows that task execution time of MTDS is about 70% faster than that of TDS in the best case and the same as the result of TDS in the worst case. It proves that MTDS method is better than TDS method.

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Design and Performance Analysis of Caching Algorithms for Distributed Non-uniform Objects (분산 이질형 객체 환경에서 캐슁 알고리즘의 설계 및 성능 분석)

  • Bahn, Hyo-Kyung;Noh, Sam-Hyeok;Min, Sang-Lyul;Koh, Kern
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.6
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    • pp.583-591
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    • 2000
  • Caching mechanisms have been studied extensively to buffer the speed gap of hierarchical storages in the context of cache memory, paging system, and buffer management system. As the wide-area distributed environments such as the WWW extend broadly, caching of remote objects becomes more and more important. In the wide-area distributed environments, the cost and the benefit of caching an object is not uniform due to the location of the object; which should be considered in the cache replacement algorithms. For online operation, the time complexity of the replacement algorithm should not be excessive. To date, most replacement algorithms for the wide-area distributed environments do not meet both the non-uniformity of objects and the time complexity constraint. This paper proposes a replacement algorithm which considers the non-uniformity of objects properly; it also allows for an efficient implementation. Trace-driven simulations show that proposed algorithm outperforms existing replacement algorithms.

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A Bayesian Inference Model for Landmarks Detection on Mobile Devices (모바일 디바이스 상에서의 특이성 탐지를 위한 베이지안 추론 모델)

  • Hwang, Keum-Sung;Cho, Sung-Bae;Lea, Jong-Ho
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.1
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    • pp.35-45
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    • 2007
  • The log data collected from mobile devices contains diverse meaningful and practical personal information. However, this information is usually ignored because of its limitation of memory capacity, computation power and analysis. We propose a novel method that detects landmarks of meaningful information for users by analyzing the log data in distributed modules to overcome the problems of mobile environment. The proposed method adopts Bayesian probabilistic approach to enhance the inference accuracy under the uncertain environments. The new cooperative modularization technique divides Bayesian network into modules to compute efficiently with limited resources. Experiments with artificial data and real data indicate that the result with artificial data is amount to about 84% precision rate and about 76% recall rate, and that including partial matching with real data is about 89% hitting rate.