• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.32-39
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• 2012

In this paper, the implementation of location based services (LBS) using S-DMB (satellite-digital multimedia broadcasting) system was proposed. In S-DMB System, the frequency of transmitted signal is about 2 GHz which has a characteristics of strong straightness but weak diffraction so that there are many shade areas such as indoors and underground spaces. Therefore the signal transmitted from the satellite should be retransmitted by the earth repeaters called as gap filler. Because each gap filler has its own identification value, the gap filler ID introduces the area in which the gap filler was installed. Generally, the 51st data symbols of S-DMB pilot signal transmitted from the satellite are padded by dummy value and gap filler ID is embedded in this pilot symbol by the gap filler when S-DMB signals are retransmitted by gap fillers. So using gap filler ID of S-DMB system, LBS such as region registration, distance and time to destination, alarm of local area information could be implemented. In the experiment to prove the performance of the proposed LBS system using the gap filler ID of the S-DMB system, the firmware of S-DMB chip composing of RF and baseband parts was lightly modified so that application processor was able to manipulate the gap filler ID and the its related regional information.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

• Journal of Broadcast Engineering
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• v.2 no.2
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• pp.86-93
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• 1997

Fast growth of multimedia applications requires new functions for video data processing. such as obj;cted-based video representation and manipulation. which are not supported by 11PEG-l and 11PEG-2. To support these requirements. 11PEG-4 video coding allows users to manipulate every video object easily by decomposing a scene into several video objects and coding each of them independently. However. the large amount of computations and flexible structure of 11PEG-4 video CODEC make it difficult to be implemented by either the general purpose DSP or a dedicated VLSI. In this paper, we propose a hardware architecture using a hybrid of a high performance programmable DSP and an application specific IC to implement a flexible 11PEG-4 video codec requiring the large amount of computations. The application specific IC has the functions of motion estimation and compensation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.13 no.1
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• pp.46-52
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• 2014

In this paper, we present a design of meander type microstrip patch antenna which has the best quality in RFID approved international standard of 910MHz broadband, usable in metal environment. In order to be fit into the commercial tag chip on the antenna, a square shaped feeder is installed on the main body as well as in the main body. In addition, a multi meander type patching element was designed in order to reduce the main body effectively. Three antennae, Cases 1, 2 and 3, were designed and compared in the areas of broad band width, effectiveness or recognition distance according to their sizes and number of folds. The measurement result of Case 3 was determined to be the best. It was confirmed that mostly the efficiency and characteristic gain change due to antenna size and number of folds in meander type influenced the antenna recognition distance.

• Journal of Korea Game Society
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• v.12 no.1
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• pp.103-111
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• 2012

Games in 1970s have used the savings of analog wavelength as in music and the like on hardwares of small cassette, gramophone, and the like. Due to these configuration elements, durability has to be declined so much. In the event of using the music on the video game, more affordable method is to use the computer chip to convert the analog sound into the computer code to convert into the electric wavelength to send to the speaker. The sound effect of the game is generated in this method. The technical limit has been gradually overcome to grant more freedom to the composers and the sound track pre-recorded on the optic disc and the like has emerged. The game developers of today have made several attempts on the technology to produce the game music. This study has contemplated the process of advancement in the change of game music production with the influence on technology and business.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.795-805
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• 2012

This paper proposes an algorithm and a hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional system, The pipelined broadcast algorithm is an algorithm which takes advantage of maximum bandwidth of communication bus. But unnecessary synchronization process are repeated, because the pipelined broadcast sends the data divided into many parts. In this paper, the MPI unit for pipeline chain algorithm based on circuit switching removing the redundancy of synchronization process was designed, the proposed architecture was evaluated by modeling it with systemC. Consequently, the performance of the proposed architecture was highly improved for broadcast communication up to 3.3 times that of systems using conventional pipelined broadcast algorithm, it can almost take advantage of the maximum bandwidth of transmission bus. Then, it was implemented with VerilogHDL, synthesized with TSMC 0.18um library and implemented into a chip. The area of synthesis results occupied 4,700 gates(2 input NAND gate) and utilization of total area is 2.4%. The proposed architecture achieves improvement in total performance of MPSoC occupying relatively small area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.814-821
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• 2012

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.