• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.51-56
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• 2006

Polymer light emitting diodes (PLEDs) with ITO/EDOT:PSS/PVK/PFO-poss/LiF/Al structures were prepared by the spin coating method on ITO(indium tin oxide)/glass substrates. PFO-poss[Poly(9,9-dioctylfluorenyl-2,7-diyl) end capped with poss] was used as light emitting polymer. PVK[poly(N-vinyl carbazole)] and PEDOT:PSS [poly(3,4-ethylenedioxythiophene):poly(styrene sulfolnate)] polymers were used as the hole injection and transport materials. The effect of PFO-poss concentration and the heating temperatures on the electrical and optical properties of the devices were investigated. At the same concentration of PFO-poss solution, the current density and luminance of PLED device tend to increase as the annealing temperature increase from $100^{\circ}C$ to $200^{\circ}C$. The maximum luminance was found to be about 958 cd/m2 at 13V for the PLED device with 1.0 wt% PFO-poss at the annealing temperature of $200^{\circ}C$. In addition, the PLED device showed bluish white emission through the strong greenish peak with 523 nm in wavelength. As the concentration of PFO-poss increase from 0.5 wt% to 1.0 wt% and temperature of PLEDs increase from $100^{\circ}C$ to $200^{\circ}C$, the emission color tend to be shifted from blue with (x, y) = (0.17,0.14) to bluish white with (x, y) : (0.29,0.41) in CIE color coordinate.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.17-24
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• 2021

Perovskite solar cells (PSCs) can be fabricated through solution process economically with variable bandgap that is controlled by composition of precursor solution. Tandem cells in which PSCs combined with silicon solar cells have potential to reach high power conversion efficiency over 30%, however, lack of long-term stability of PSCs is an obstacle to commercialization. Degradation of PSCs is mainly attributed to the mass transport of halide and metal electrode materials. In order to ensure the long-term stability, the mass transport should be inhibited. In this study, we confirmed degradation behaviors due to the mass transport in PSCs and designed buffer layers with LiF and/or SnO₂ to improve the long-term stability by suppressing the mass transport. Under high-temperature storage test at 85℃, PSCs without the buffer layers were degraded by forming PbI₂, AgI, and the delta phase of the perovskite material, while PSCs with the buffer layers showed improved stability with keeping the original phase of the perovskite. When the LiF buffer and encapsulation were applied to PSCs, superior long-term stability on 85℃-85% RH dump heat test was achieved; efficiency drop was not observed after 200 h. It was also confirmed that 90.6% of the initial efficiency was maintained after 200 hours of maximum power tracking test under AM 1.5G-1SUN illumination. Here, we have demonstrated that the buffer layer is essential to achieve long-term stability of PSCs.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.49-53
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• 2018

Since various methods to form well-aligned nano-/micro- patterns are underlying technologies to fabricate next generation wearable electronic devices, many efforts have been made to realize finer patterns in recent years. Among lots of patterning methods, the present invention includes a nano-transfer printing (n-TP) process which is advantageous in that a processing cost is low and high-resolution patterns can be formed within a short processing time. We successfully achieved pattern formation of highly ordered Pt lines with line-width of 250 nm, 500 nm, and $1{\mu}m$ on transparent and flexible substrates. In addition, we analyzed the durability of the patterns, showing excellent stability of line-shape even after a physical and repeated bending test of 500 times using a bending machine. As a result, it is expected that a n-TP process is very useful for forming various metal patterns, and it is also expected to be applied to wiring and interconnection technology of next generation flexible electronic devices.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.10
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• pp.1189-1193
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• 2012

The Miniaturized Fingerprint Imager (MFI) is a slim optical mouse that can be used as an input device for application to wireless portable personnel communication devices such as smartphones. In this study, we have fabricated key optical components of an MFI, including the illumination optical components and imaging lens. An LED beam-shaping lens consisting of an aspheric lens and a Fresnel facet was successfully machined using a diamond turning machine (DTM). A customized V-shaped groove for beam path banding was fabricated by the bulk micromachining of silicon that was coated with aluminum using the shadow effect in thermal evaporation. The imaging lens and arrayed multilevel Fresnel lenses were fabricated by electron beam lithography and FAB etching, respectively. The proposed optical components are extremely compact and have high optical efficiency; therefore, they are applicable to ultraslim optical systems.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.107-107
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• 2000

최근 반도체 소자의 고집적화 및 대용량화의 경향에 다라 MOSFET 소자 제작에 이동되는 게이트 산화막의 두께가 수 nm 정도까지 점점 얇아지는 추세이고 Giga-DRAM급 차세대 UNSI소자를 제작하기 위해 5nm이하의 게이트 절연막이 요구된다. 이런 절연막의 두께감소는 게이트 정전용량을 증가시켜 트랜지스터의 속도를 빠르게 하며, 동시에 저전압동작을 가능하게 하기 때문에 게이트 산화막의 두께는 MOS공정세대가 진행되어감에 따라 계속 감소할 것이다. 따라서 절연막 두께는 소자의 동작 특성을 결정하는 중요한 요소이므로 이에 대한 정확한 평가 방법의 확보는 공정 control 측면에서 필수적이다. 그러나, 절연막의 두께가 작아지면서 게이트 산화막과 crystalline siliconrksm이 계면효과가 박막의 두께에 심각한 영향을 주기 때문에 정확한 두께 계측이 어렵고 계측방법에 따라서 두께 계측의 차이가 난다. 따라서 차세대 반도체 소자의 개발 및 양산 체계를 확립하기 위해서는 산화막의 두께가 10nm보다 작은 1nm-5nm 수준의 박막 시료에 대한 두께 계측 방법이 확립이 되어야 한다. 따라서, 본 연구에서는 습식 산화 공정으로 제작된 3nm-7nm 의 게이트 절연막을 현재까지 알려진 다양한 두께 평가방법을 비교 연구하였다. 절연막을 MEIS (Medim Energy Ion Scattering), 0.015nm의 고감도를 가지는 SE (Spectroscopic Ellipsometry), XPS, 고분해능 전자현미경 (TEM)을 이용하여 측정 비교하였다. 또한 polysilicon gate를 가지는 MOS capacitor를 제작하여 소자의 Capacitance-Voltage 및 Current-Voltage를 측정하여 절연막 두께를 계산하여 가장 좋은 두께 계측 방법을 찾고자 한다.다. 마이크로스트립 링 공진기는 링의 원주길이가 전자기파 파장길이의 정수배가 되면 공진이 일어나는 구조이다. Fused quartz를 기판으로 하여 증착압력을 변수로 하여 TiO2 박막을 증착하였다. 그리고 그 위에 은 (silver)을 사용하여 링 패턴을 형성하였다. 이와 같이 공진기를 제작하여 network analyzer (HP 8510C)로 마이크로파 대역에서의 공진특서을 측정하였다. 공진특성으로부터 전체 품질계수와 유효유전율, 그리고 TiO2 박막의 품질계수를 얻어내었다. 측정결과 rutile에서 anatase로 박막의 상이 변할수록 유전율은 감소하고 유전손실은 증가하는 결과를 나타내었다.의 성장률이 둔화됨을 볼 수 있다. 또한 Silane 가스량이 적어지는 영역에서는 가스량의 감소에 의해 성장속도가 둔화됨을 볼 수 있다. 또한 Silane 가스량이 적어지는 영역에서는 가스량의 감소에 의해 성장속도가 줄어들어 성장률이 Silane가스량에 의해 지배됨을 볼 수 있다. UV-VIS spectrophotometer에 의한 비정질 SiC 박막의 투과도와 파장과의 관계에 있어 유리를 기판으로 사용했으므로 유리의투과도를 감안했으며, 유리에 대한 상대적인 비율 관계로 투과도를 나타냈었다. 또한 비저질 SiC 박막의 흡수계수는 Ellipsometry에 의해 측정된 Δ과 Ψ값을 이용하여 시뮬레이션한 결과로 비정질 SiC 박막의 두께를 이용하여 구하였다. 또한 Tauc Plot을 통해 박막의 optical band gap을 2.6~3.7eV로 조절할 수 있었다. 20$0^{\circ}C$이상으로 증가시켜도 광투과율은 큰 변화를 나타내지 않았다.부터 전분-지질복합제의 형성 촉진이 시사되었다.이것으로 인하여 호화억제에 의한 노화 방지효과가 기대되었지만 실제로 빵의 노화는 현저히 진행되었다

• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.65-70
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• 2023

Nanoimprint lithography (NIL) has attracted much attention due to its process simplicity, excellent patternability, process scalability, high productivity, and low processing cost for pattern formation. However, the pattern size that can be implemented on metal materials through conventional NIL technologies is generally limited to the micro level. Here, we introduce a novel hard imprint lithography method, extreme-pressure imprint lithography (EPIL), for the direct nano-to-microscale pattern formation on the surfaces of metal substrates with various thicknesses. The EPIL process allows reliable nanoscopic patterning on diverse surfaces, such as polymers, metals, and ceramics, without the use of ultraviolet (UV) light, laser, imprint resist, or electrical pulse. Micro/nano molds fabricated by laser micromachining and conventional photolithography are utilized for the nanopatterning of Al substrates through precise plastic deformation by applying high load or pressure at room temperature. We demonstrate micro/nanoscale pattern formation on the Al substrates with various thicknesses from 20 ㎛ to 100 mm. Moreover, we also show how to obtain controllable pattern structures on the surface of metallic materials via the versatile EPIL technique. We expect that this imprint lithography-based new approach will be applied to other emerging nanofabrication methods for various device applications with complex geometries on the surface of metallic materials.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.62-75
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• 2007

This paper describes a shaped-beam antenna for increasing the antenna gain of a radiating element. The proposed antenna structure is composed of an exciting element and a multi-layered disk array structure(MDAS). The stack micro-strip patch elements were used as the exciter for effectively radiating the electromagnetic power to the MDAS over the broadband, and finite metallic disk array elements - which give the role of a director for shaping the antenna beam with the high gain - were finitely and periodically layered onto it. The efficient power coupling between the exciter and the MDAS should be carried out in such a way that the proposed antenna has a high gain characteristic. The design parameters of the exciter and the MDAS should be optimized together to meet the required specifications to meet the required specifications. In this study, a shaped-beam antenna with high gain was optimally designed under the operating conditions with a linear polarization and the frequency band of $9.6{\sim}10.4\;GHz$. Two methods constructed using thin dielectric film and dielectric foam materials respectively were also proposed in order to implement the MBAS of the antenna. In particular, through the computer simulation process, the electrical performance variations of the antenna with the MDAS realized by the thin dielectric film materials were shown according to the number of disk array elements in the stack layer. Two kinds of antenna breadboard with the MDAS realized with the thin dielectric film and dielectric foam materials were fabricated, but experimentation was conducted only on the antenna breadboard(Type 1) with the MDAS realized with the thin dielectric film materials according to the number of disk array elements in the stack layer in order to compare it with the electrical performance variations obtained during the simulation. The measured antenna gain performance was found to be in good agreement with the simulated one, and showed the periodicity of the antenna gain variations according to the stack layer number of the disk array elements. The electrical performance of the Type 1 antenna was measured at the center frequency of 10 GHz. As the disk away elements became the ten stacks, a maximum antenna gain of 15.65 dBi was obtained, and the measured return loss was not less than 11.4 dB within the operating band. Therefore, a 5 dB gain improvement of the Type 1 antenna can be obtained by the MDAS that is excited by the stack microstrip patch elements. As the disk array elements became the twelve stacks, the antenna gain of the Type 1 was measured to be 1.35 dB more than the antenna gain of the Type 2 by the outer dielectric ring effect, and the 3 dB beam widths measured from the two antenna breadboards were about $28^{\circ}$ and $36^{\circ}$ respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1294-1302
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• 2008

A design approach for a radiation element of dual polarization, which can be implemented in the waveguide structure, is proposed. For minimization of the radiating element, the ridged waveguide type is used and for dual polarization, the microstrip type of printed dipole structure is additionally installed inside the waveguide. In order to validate the design approach, $1{\times}4$ array antenna is fabricated and its performances such as return loss, co-polarization coupling between adjacent channels, and radiation patterns are investigated. Theory and experiment are observed to be in good agreement. The radiating structure is thought to be a useful one in an application to the phased array antenna system, in particular, requiring dual polarization characteristics.

• Journal of Engineering Education Research
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• v.2 no.1
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• pp.10-16
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• 1999

In this paper, we developed the internet-based educational software package (DVLab) for design and virtual experiment of the digital logic circuits. The DVLab consists of the LogicSim module for design and simulation of digital combinational/sequantial logic circuits, micro-controller application circuits and the BreadBoard module for virtual experiment and the Theory module for lecture and the Report/ReportChecker module and some other utility modules. All developed modules can be run as application programs as well as applets in the Internet. The LogicSim and the BreadBoard support real time clock function, output verification function on the designed circuits, trace function of logic values, copy-protection function of designed circuits and provide various devices including logic gates, TTLs, LED, buzzer, and micro-controller. The educational model of digital logic circuit design and experiment using the DVLab is also presented in this paper.