• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.178-179
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• 2005

ESD(Electrostatic Discharge) 보호에 응용되는 소자는 ESD가 발생했을 때, 빠르게 턴-온되어 외부로부터 EOS(Electric OverStress)를 차단함으로서 집적회로 내부의 코어를 보호해 주어야 한다. 이러한 기능에 충실한 LVTSCR(Low-Voltage Silicon Controlled Rectifier)은 트리거링 전압을 기존의 SCR보다 낮추어 ESD에 대해 민감한 반응을 할 수 있도록 개선한 소자이다. 그러나 트리거링 전압을 낮추면서 래치업 전압 또한 낮아지는 특성이 trade-off 관계로 맞물려 있어, LVTSCR의 단점인 낮은 래치업 전압을 효과적으로 다루는 것이 큰 이슈가 되고 있다. 본 논문에서는 LVTSCR의 ESD 보호에 대한 응용시 발생 가능한 래치업을 차폐하는 회로적 방법을 제시하였다. 제시된 새로운 구조의 차폐회로는 LVTSCR에서 래치업이 발생했을 때, 천이 전류를 감지하여 래치업이 발생되는 소자에 대한 전원을 스스로 차폐시켜 래치업에 대한 안정성을 시뮬레이션으로 검증하였다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2012.10a
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• pp.391-392
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• 2012

항로표지의 원격 관리를 VHF, CDMA, TRS의 경로설정 최적화(Path Optimization) 기능을 갖는 하이브리드 통신을 이용하면 개별 통신 방식별로 음영지역이 존재하는 경우에도, 최적의 통신방식을 선택하여 통신을 수행하게 됨으로써, 통신 음영지역의 해소가 가능하다. 또한 통신장치마다 동일한 데이터 프레임을 사용함으로써 데이터의 호환성을 높였다. 실험은 30일 동안 각 부표에서 매 5분마다 데이터를 취득하였으며, 데이터 수신율은 99.4 % 이상을 보였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.54-61
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• 1998

A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.556-558
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• 2004

최근 VLSI 설계 분야에서, 단열 논리는 에너지 효율성이 뛰어난 저전력 설계 기술 중 하나로 각광 받고 있다. 이러한 단열 논리는 기존의 저전력 회로 설계를 위해 사용되었던 CMOS 논리들을 서서히 대체해 나갈 컷으로 기대되고 있다. 하지만 않은 단열 논리들의 제시에도 불구하고, 기존의 CMOS논리들을 단열 논리로 대체하는 기법에 관한 연구는 거의 없는 실정이다. 이 논문에서는 래치형 패스 트랜지스터 단열 논리(LPAL)와 이를 이용한 저전력 설계 기법을 소개하였다. 래치형 패스 트랜지스터 단열 논리는 기존의 단열 논리들이 가지고 있는 단정을 해결하고, 보다 저전력 지향적으로 CMOS논리를 대체 할 수 있다는 장점을 가진다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• Journal of IKEEE
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• v.18 no.1
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• pp.25-30
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• 2014

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.72-84
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• 2001

The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.1
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• pp.54-57
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• 2005

A soft error rate neutrons is a growing problem fur terrestrial integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.