• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
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• 2008.04a
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• pp.69-75
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• 2008

기포반응도는 월성발전소를 비롯한 CANDU형 원자로의 주된 안전성 쟁점사안으로 끊임없이 논의되어 왔다. 이는 설계기준사고가 노심에서 열에너지 불균형이 원인이 되어 기준이상의 핵연료 파손과 방사성물질 누출로 발전할 위험이 있는 사건들로 정의될 때, 사건 진행 과정에 기포반응도 증가는 조기에 운전중단을 실패할 경우 출력폭주로 이어지므로 사건의 결말이 중대사고로 전환될 위험이 크기 때문이다. 본 연구는 공개된 최신 핵자료인 ENDF/B-VII.0를 NJOY.99로 처리한 연속에너지 반응단면적 라이브러리를 구축하고 MCNP-4C에 접속하여 37봉 천연우라늄 핵연료다발의 표준노심격자에 대한 기포반응도를 시뮬레이션하여, 지금까지 각종문헌에 제시된 값들과 비교, 종합하므로 내제된 불확실성을 추정하는 내용이다. ENDF/B-VII.0 기반 MCNP-4C의 CANDU 노심격자 모델은 동일한 핵자료와 핵종농도를 사용한 WIMS-IAEA 모델과 비교할 때, 초기 노심의 임계도 오차 약 3.51mk가 연소 진행에 따라 $7.5\times10^{-4}mk$/MWD/teU의 비율로 감소하는 것으로 나타났다. 또한 MCNP-4C 예측기포반응도는 초기노심에서 기포율 50% 및 100%에 대해 각각 8.38 및 15.96mk, 평형노심에서 7.68 및 14.72mk로 계산된다. 이는 월성 2, 3, 4 FSAR의 초기노심 및 평형노심에서 100% 기포상태에 대한 값, 약15.0 및 10.6mk와 비교할 때, 초기노심은 약 1.0mk 평형노심은 약4, 1mk 보수적이지만, 다른 연구결과들과는 최대오차 ${\pm}1{\sim}2mk$ 이내에서 잘 일치하는 것으로 평가되었다. 본 연구는 CANDU 노심의 기포반응도 불확실성 요인의 규명 및 영향평가를 위한 노력의 일부로서 앞으로 감속재의 붕산농도 변화, 감속재 및 냉각재의 중수 순도 변화, 기기노화에 의한 격자 구조 및 물성 변화, 중성자속 및 출력 분포 불균형, 반응도조절장치의 위치, 등 주요 설계변수의 변화에 대한 반응도영향 분석연구를 계속할 계획이다.

• Journal of Conservation Science
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• v.36 no.2
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• pp.73-81
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• 2020

Considering the difficulties associated with the creation of deterioration maps for stone cultural heritages, quantitative determination of chemical and biological contaminants in them is still challenging. Hyperspectral image analysis has been proposed to overcome this drawback. In this study, hyperspectral imaging was performed on Stone Buddhas Temple in Four Directions at Gulbulsa Temple Site(Treasure 121), and several surface contaminants were observed. Based on the color and shape, these chemical and biological contaminants were classified into ten categories. Additionally, a method for establishing each class as a reference image was suggested. Simultaneously, with the help of Spectral Angle Mapper algorithm, two classification methods were used to classify the surface contaminants. Method A focused on the region of interest, while method B involved the application of the spectral library prepared from the image. Comparison of the classified images with the reference image revealed that the accuracies and kappa coefficients of methods A and B were 52.07% and 63.61%, and 0.43 and 0.55, respectively. Additionally, misclassified pixels were distributed in the same contamination series.

• Korean Journal of Soil Science and Fertilizer
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• v.41 no.4
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• pp.267-272
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• 2008

Mid-infrared (MIR) spectroscopy, particularly Fourier transform infrared spectroscopy (FTIR), has emerged as an important analytical tool in quantification as well as identification of multi-atomic inorganic ions such as nitrate. In the present study, the possibility of quantifying soil nitrate via diffuse reflectance infrared Fourier transform spectroscopy (DRIFTS) without change of a sample phase or with least treated samples was examined. Four types of soils were spectrally characterized in terms of unique bands of soil contents and interferences with nitrate bands in the range of $2000-1000cm^{-1}$. In order to reduce the effects of soil composition on calibration model for nitrate, spectra transformed to the 1st order derivatives were used in the partial least squared regression (PLSR) model and the classification procedure associated with input soil types was involved in calibration system. PLSR calibration models for each soil type provided better performance results ($R^2$>0.95, RPD>6.0) than the model considering just one type of soil as a standard.

• Journal of the Korea Society of Computer and Information
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• v.29 no.7
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• pp.33-40
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• 2024

The live weight of livestock is important information for managing their health and housing conditions, and it can be used to determine the optimal amount of feed and the timing of shipment. In general, it takes a lot of human resources and time to weigh livestock using a scale, and it is not easy to measure each stage of growth, which prevents effective breeding methods such as feeding amount control from being applied. In this paper, we aims to improve the accuracy of weight measurement of piglets, weaned pigs, nursery pigs, and fattening pigs by collecting, analyzing, learning, and predicting video and image data in animal husbandry and pig farming. For this purpose, we trained using Pytorch, YOLO(you only look once) 5 model, and Scikit Learn library and found that the actual and prediction graphs showed a similar flow with a of RMSE(root mean square error) 0.4%. and MAPE(mean absolute percentage error) 0.2%. It can be utilized in the mammalian pig, weaning pig, nursery pig, and fattening pig sections. The accuracy is expected to be continuously improved based on variously trained image and video data and actual measured weight data. It is expected that efficient breeding management will be possible by predicting the production of pigs by part through video reading in the future.

• Journal of the Korean Association of Geographic Information Studies
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• v.10 no.3
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• pp.113-122
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• 2007

The rapid growth of aerial survey and remote sensing technology has enabled the rapid acquisition of very large amounts of geographic data, which should be analyzed using real-time visualization technology. The level of detail(LOD) algorithm is one of the most important elements for realizing real-time visualization. We chose the triangulated irregular network (TIN) method to generate normalized digital elevation model(DEM) data. First, we generated TIN data using contour lines obtained from a two-dimensional(2D) digital map and created a 2D grid array fitting the size of the area. Then, we generated normalized DEM data by calculating the intersection points between the TIN data and the points on the 2D grid array. We used constrained Delaunay triangulation(CDT) and ray-triangle intersection algorithms to calculate the intersection points between the TIN data and the points on the 2D grid array in each step. In addition, we simulated a three-dimensional(3D) terrain model based on normalized DEM data with real-time visualization using a Microsoft Visual C++ 6.0 program in the DirectX API library and a quad-tree LOD algorithm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.213-220
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• 2011

In this paper, the channel preprocessor with an area-efficient architecture is proposed for the MIMO symbol detector which can support four transmit and receive antennas. The proposed channel preprocessor can shrink the channel dimension to reduce the hardware complexity of the MIMO symbol detector. Also, the proposed channel preprocessor is implemented with very low complexity by using QR decomposition (QRD) and log-number system (LNS). By applying QRD and LNS to the nulling matrix calculation block, the numbers of matrix-multiplications and matrix-divisions are decreased and thus the complexity of the proposed channel preprocessor is significantly reduced. The proposed channel preprocessor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed channel preprocessor, the number of logic gates for channel preprocessor is reduced by 20.2% compared with the conventional architecture.