• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.860-868
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• 2011

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. In this paper, we propose a SPN block cipher so called SSB which has a symmetric structure in encryption and decryption. The proposed SSB is composed of the even numbers of N rounds. Each round consists of a round key addition layer, a subsitution layer, a byte exchange layer and a diffusion layer. The subsitution layer of the odd round is inverse function of one of the even round. And the diffusion layer is a MDS involution matrix. The differential and linear attack probability of SSB is $2^{-306}$ which is same with AES. The proposed symmetric SPN block cipher SSB is believed to construct a safe and efficient cipher in Smart Card and RFID environments which is in limited hardware and software resources.

• The Journal of the Acoustical Society of Korea
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• v.30 no.6
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• pp.337-343
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• 2011

With commencing trial 3D digital broadcasting, the studies on next generation digital broadcasting technology for coming UHDTV era is being actively progressing. In this paper, I propose surround audio formats for next-generation digital TV broadcasting, along with comparative study of major surround audio formats in use or under development. I did comparative study on current major competing surround formats such as Dolby True HD and DTS HD MA, along with NHK proposed 22.2 channel surround format for UHDTV system. Upon this comparative study and our housing situation consideration, I propose lossy compression 3D surround 7.1 channel surround format along with loosless 2.0 and 4.0 hi-fi format as next generation digital TV broadcasting standard. In lieu with this, I also propose transmitting binaural 2 channel audio data as sub-audio. It will give holographic sound experience when properly processed with individual HRTF (Head Related Transfer Function) with headphone. The table for data rate of each proposed audio format is also presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.107-111
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• 2005

As Internet grows rapidly and next electronic commerce applications increase, the security is getting more important. Information security to provide secure and reliable information transfer is based on cryptography technique. The proposed ISEED(Improved SEED) algorithm based on block cryptography algorithm which belongs to secret-key algorithm. In terms of efficiency, the round key generation algorithm has been proposed to reduces the time required in encryption and decryption. The algorithm has been implemented as follow. 128-bit key is divided into two 64-bit group to rotate each of them 8-bit on the left side and right side, and then basic arithmetic operation and G function have been applied to 4-word outputs. In the process of converting encryption key which is required in decryption and encryption of key generation algorithm into sub key type, the conversion algorithm is analyzed. As a result, the time consumed to encryption and decryption is reduced by minimizing the number of plain text required differential analysis.

• Journal of Korea Multimedia Society
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• v.11 no.8
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• pp.1093-1100
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• 2008

Feistel and SPN are the two main structures in designing a block cipher algorithm. Unlike Feistel, an SPN has an asymmetric structure in encryption and decryption. In this paper we propose an SPN algorithm which has a symmetric structure in encryption and decryption. The whole operations in our SPN algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2, applies function and the last half of them, (N+1)/2 to N, employs inverse function. Symmetry layer is executed to create a symmetry block in between function layer and inverse function layer. AES encryption and decryption algorithm, whose safety is already proved, are exploited for function and inverse function, respectively. In order to be secure enough against the byte or word unit-based attacks, 32bit rotation and simple logical operations are performed in symmetry layer. Due to the simplicity of the proposed encryption and decryption algorithm in hardware configuration, the proposed algorithm is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2010.04a
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• pp.201-206
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• 2010

A project for construction of Korea Geodetic VLBI has officially started in Oct. 2008. The construction of all system will be completed by the end of 2011. The project was named Korea VLBI system for Geodesy (KVG), and its main purpose is to maintain the Korea Geodetic Datum. In case of the KVG system, an observation room where an H-maser frequency standard is located is in a building separated from an antenna by several tens of meters. Therefore KVG system will adopt a so-called round-trip system to transmit reference signals to the antenna with diminishing the effect of path length variations. KVG's round-trip system is designed not only available to use either metal or optical fiber cables, but also available to measure path length variations directly by using K5/VSSP32 sampler. We will present principle of round-trip system and the new type of round trip system for KVG.

• Journal of KIISE:Information Networking
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• v.32 no.6
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• pp.676-686
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• 2005

The Internet users as well as network providers are eager to have different qualities of service among users beyond the best-effort. In this paper, we propose a scheduling algorithm that provides a differentiated service in the granularity of user sessions. The proposed algorithm is a Hierarchical Deficit Round-Robin (H-DRR) algorithm that is an extension of an existing DRR algorithm. A main advantage is that H-DRR provides service differentiation for throughput-intensive applications such as FTP as well as delay-sensitive applications such as telnet or VoIP without distinguishing the types of applications. The most importance in providing a service differentiation in term of network providers is to have controllability and predictability. We show that H-DRR is superior to DRR in terms of controllability and predictability through both mathematical analysis and simulation experiments. Nevertheless, H-DRR requires O(1) complexity for implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1207-1214
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• 2002

A scheduling scheme for high speed networks requires a low time complexity to schedule packets in a packet transmission time. High speed networks support a number of connections, different rates for each connection and variable packet length. Conventional round robin algorithms have a time complexity of O(1), but their short time fairness, latency and burstiness depend on the quantum of a connection due to serving several packets for a backlogged connection once a round. To improve these properties, we propose in this paper an efficient packet scheduling scheme which is based on the credits of a connection and has a time complexity of O(1). We also analyzed its performance in terms of short time fairness, latency and burstiness. The analysis results show that the proposed scheme can improve the performance compared with traditional round robin schemes. The proposed scheme can be easily utilized in high speed packet networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.351-358
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• 2016

This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.