• Proceedings of the Optical Society of Korea Conference
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• 2009.02a
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• pp.215-216
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• 2009

• Proceedings of the Optical Society of Korea Conference
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• 2008.02a
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• pp.135-136
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• 2008

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.6
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• pp.25-30
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• 2013

In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.11-17
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• 2002

This paper describes on a position detection method for the motors which have repetitive operations using the Algorithmic State Machine(ASM), one of the digital logic design methods. With analyses for the incremental encoder output patterns, state diagram and state table are constructed and a digital circuit which can detect the changing point of direction of motor rotation is designed. To verify the validity of the designed circuit, simulations for all cases in which the direction of motor rotation is changed, are performed. Simulation results show the designed digital circuit can detect the direction of motor rotation accurately for all cases.

• The Journal of Information Technology
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• v.4 no.3
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• pp.155-163
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• 2001

In this paper, we implemented sigmoid active function which make it difficult to design of the digital neuron networks. Therefore, we designed of the high speed processing of the sigmoid function in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. we designed of MAC operation unit and sigmoid processing unit are proved that it could run of the high speed. On the simulation, the faster than 4.6ns on the each order, we expected that it adapted to the implementation of the high speed digital neural network.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.5
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• pp.122-131
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• 1999

저주파의 아날로그 신호를 디지털 신호로 변환하기 위해 sigma-delta 아날로그-디지털 변환기의 이용이 용이하다. 이 변환기는 변조기와 디지털 필터로 구성되는데 본 논문에서는 변조기에 대해서만 언급한다. 모델링을 통해 14비트 분해능을 갖는 2차 sigma-delta 변조기를 설계하기 위한 변조기의 구성요소 즉 연산 증폭기, 적분기, 내부 ADC 및 DAC의 최대 허용 에러 범위를 규정하였으며, 이를 토대로 연산증폭기, 2비트 ADC 및 DAC 등을 설계·검증하고, 이들을 서로 연결하여 2차 sigma-delta 변조기를 구성하였다. 3비트 ADC의 기준전압을 조절하여 변조기 성능 향상을 도모하였으며, 내부 DAC를 축전기 및 간단한 제어회로로 구성하여 비선형성 에러를 최소화하였다. 설계된 각각의 구성요소들은 모델링에서 정의된 에러 범위를 모두 만족하였으며, 전체 변조기는87㏈의 입력범위와 87㏈의 최대 신호 대 잡음 비를 가졌다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.96-102
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• 1998

This paper describes the design of the digital controller for Full-Bridge Phase-shifted converter with zero-voltage switching (ZVS). Although digital control techniques are widely used in the area of inverters and motor drives, their use for the control of high-frequency switching power supply is still rare. Therefore, this paper presents design method of digital controller of Full-Bridge Phase-shifted converter with zero-voltage switching (ZVS) and compares with conventional analog controller. The controller design is optimized by running computer simulation with the MATLAB numerical calculation package.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.6
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• pp.44-52
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• 2017

In this paper, we propose a DFD (Digital Frequency Discriminator) design that has better frequency discrimination and a smaller size. Electronic warfare equipment can analyze different types of radar signal such as those based on Frequency, Pulse Width, Time Of Arrival, Pulse Amplitude, Angle Of Arrival and Modulation On Pulse. In order for electronic warfare equipment to analyze radar signals with a narrow pulse width (less than 100ns), they need to have a special receiver structure called IFM (Instantaneous Frequency Measurement). The DFD (Digital Frequency Discriminator) is usually used for the IFM. Because the existing DFDs are composed of separate circuit devices, they are bulky, heavy, and expensive. To remedy these shortcomings, we use a three delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$) in the DFD, instead of the four delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$, $64{\lambda}$) generally used in the existing DFDs, and apply the microwave integrated circuit method. To enhance the frequency discrimination, we detect the pulse amplitude and perform temperature correction. The proposed DFD has a frequency discrimination error of less than 1.5MHz, affording it better performance than imported DFDs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.37-42
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• 2010

A novel hysteresis tunable monolithic comparator circuit based on a $0.35{\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V.