• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.87-93
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• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.43-52
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• 2016

Wireless sensor network (WSN) technology has been implemented using commercial off-the-shelf microcontrollers (MCUs), In this paper, we propose a simulation environment to realize the physical evaluation of FPGA-based node by considering vertically cross-layered WSN in terms of physical node device and network interconnection perspective. The proposed simulation framework emulates the physical FPGA-based sensor nodes to interoperate with the NS3 through the runtime infrastructure (RTI). For the emulation and interoperation of FPGA-based nodes, we extend a vendor-providing FPGA design tool from the host computer and a script to execute the interoperation procedures. The standalone NS-3 is also revised to perform interoperation through the RTI. To resolve the different time-advance mechanisms between the FPGA emulation and event-driven NS3 simulation, the pre-simulation technique is applied to the proposed environment. The proposed environment is applied to IEEE 802.15.4-based low-rate, wireless personal area network communication.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.454-461
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• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

• Journal of Broadcast Engineering
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• v.12 no.3
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• pp.230-241
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• 2007

This paper presents the requirements analysis for the Terrestrial DMB Automatic Emergency Alert Service (AEAS) Standard. First, the basic concepts in disaster management and the AEAS system structure are presented as a background. Next, other emergency alert systems and the related standards are analyzed. We propose taxonomy to categorize the emergency alert systems and analyze the characteristics of each system. Next, we analyze advantages of T-DMB for the delivery medium of emergency alert message and problems to resolve for the enhanced performance. Finally, we propose service requirements which will achieve general/special-purpose, non-interrupting, location-adaptive, automatic, message delivery service. The paper will contribute as a guideline to the development for emergency alert service standards for other broadcasting media.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• Journal of Broadcast Engineering
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• v.21 no.6
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• pp.944-956
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• 2016

In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.1-8
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• 2009

In this paper, a temperature variation-insensitive power-up detector for use in analog and digital integrated systems has been proposed. To provide temperature-insensitive characteristic, nMOS and pMOS voltage dividers in the proposed power-up detector are made to have zero temperature coefficient by exploiting the fact that the effective gate-source voltage of a MOS transistor can result in mutual compensation of mobility and threshold voltage for temperature independency. Comparison results using a 68-nm CMOS process indicate that the proposed power-up detector achieves as small as 4 mV voltage variation at 1.0 V power-up voltage over a temperature range of $-30^{\circ}C$ to $90^{\circ}C$, resulting in 92.6% reduction on power-up voltage variations over conventional power-up detectors.

• Journal of Digital Convergence
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• v.16 no.4
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• pp.167-173
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• 2018

The aim of the study is to examine the effects of the peer relationship promotion convergence program on self-esteem and sociality of children using a community child center. A nonequivalent control group pre-post design was used. Participants were 52 children (experimental group=26, control group=26), 4-6th grade in elementary school from 5 rural community child center. The experimental group participated in 12 sessions of the program for 50 min, once a week. The data were analyzed with descriptive statistics, a chi-square test, and an independent t-test using SPSS WIN 21.0 program. After completion of the program, the experimental group showed a significant improvement in self-esteem(t=2.43, p=.018) and sociality (t=2.03, p=.047) compared to the control group. The result shows that the program is beneficial for improving self-esteem and sociality of low-income, school-age children. Therefore, the program is recommended the intervention for improvement of self-concept and sociality of children.