• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.2
• /
• pp.152-158
• /
• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.11
• /
• pp.27-33
• /
• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.37 no.3
• /
• pp.45-55
• /
• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.5
• /
• pp.207-215
• /
• 2014

In this paper, we propose a Micro Real-Time Control System (MRTCS) for decreasing the delay during interrupts processing and data transfer on sensor nodes. The MRTCS consists of a control, sensor nodes based on Controller Area Network (CAN) device. The control node was designed with Real Time Operating System (RTOS) on top of the small Micro Control Unit (sMCU). Sensor nodes have the CAN device without sMCU, which have multiple Digital Inputs, Outputs (DI/DO) and the CAN controller. We have evaluated with OCTAVE v3.6.4 from open source for system performance. Simulation results show that the system performance was increased through the delay reducing for interrupt processing and internal data transfer. We verify that a proposed MRTCS approach will be adapted to various real-time control system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.2
• /
• pp.323-329
• /
• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.16-23
• /
• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.7
• /
• pp.1653-1659
• /
• 2013

In this paper, we propose a new ECAD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (Signal Propagation Diagram) to show internal interconnections. It is more important function that same objects in different views(HDL codes, object tree, instance tree, SPD, waveform etc.) can be highlighted at the starting any object. These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.

• Journal of KIISE:Software and Applications
• /
• v.36 no.1
• /
• pp.30-44
• /
• 2009

Devices of home network system have different control data formats according to each product company. Therefore, types or protocols of digital devices are various. Also, interaction operating environments are different among various devices. These characteristics of home network system don't support sufficiently functionalities such as data comparability, concurrent control, dynamic plug-in, and so on. That is, the degree of reusability of home network system is very poor. This paper proposes a framework which can be coverable to the scope of reusability widely and a design technique based on framework in order to improve reusability. That is, we extract various parts of home network systems as variation points, classify and define these as variation types, propose a framework which can be reusable those, and proposes a design technique of variability to improve reusability. Finally, proposed technique can be reusable to various domains by applying proposed reusability framework into real home network system's design.

• Korean Journal of Optics and Photonics
• /
• v.15 no.5
• /
• pp.423-428
• /
• 2004

The development of a compact and high performance MWIR thermal imaging sensor based on the SOFRADIR 320${\times}$240 element IRCCD detector is described. The sensor has 20 magnification zoom optics with the maximum 40$^{\circ}$${\times}$30$^{\circ}$ of super wide field of view and 7.6 cycles/mrad of resolving power with the operation of attached micro-scanning system. In order to correct nonuniformities of detector arrays, we have proposed a multi-point correction method using defocusing of the optics and we have acquired the highest quality images. The MRTD of our system shows good results below 0.05K at spatial frequency 1 cycles/mrad at narrow field of view. Experimental data and obtained performances are presented and discussed.

• Journal of Digital Convergence
• /
• v.11 no.4
• /
• pp.383-389
• /
• 2013

The purpose of this study was to investigate evidence-based practice (EBP) for sensory integration (SI) intervention in children with cerebral palsy (CP) through a systematic review and meta analysis. The screening strategy was performed to select studies for analysis after that, a meta-analysis was implemented for calculating the effect size (ES) in group studies. Twenty-four studies were included for a systematic review and included seven case reports, three single-subject designs, and fourteen group experimental design studies(three randomized controlled trials, three two groups nonrandomized studies, and six one group nonrandomized studies). The ES of the experimental group studies was moderate size of 0.272. The results of the ES according to the dependent variables, the ES was the largest in the fine motor development. The effect size of the published papers was greater than the unpublished paper's and two groups nonrandomized studies' size effect was the largest in the design. The ES of the infants was larger than the children. The ES for a period of 8 weeks, the number of five times a week, and time in 90 minutes showed the biggest in SI program. Although the ES of SI intervention in children with CP showed moderate effect, accumulation of research well be needed.