• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.40-47
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• 1998

The optical heads as the key parts of digital audio/video players are applied extensively from general household electric appliances to computer memory or game apparatuses, and the demand of them tends to be increased according to the extension of optical medium market. In this paper, the 2-axis actuator, the key component for focus servo and tracking servo of the optical head is designed as a type of the cantilever suspended by 4 wires. The design propriety is verified through its simulation and the characteristic analysis of its mock-ups. The other factors which influence the performance of 2-axis actuators besides the design factors of them, are also verified through the mock-up analysis.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.1-6
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• 2010

In this paper, it is designed a processor using embedded system so that moving picture can be expressed on LED electric sign board which has been expressed a simple message only like as a character or graphic. It has been fabricated a moving picture LED electric sign board which is composed to a video processor and LED display panel, in order to be able to express a digital moving picture of 24 bits that is transmitted from embedded system. It includes gamma adjustment, brightness, color contrast control, a schedule function, expression image conversion by the Internet and memory device. Also, an application program based Windows CE is designed so that a character, graphic, and moving picture can be expressed on a small LED electric sign board.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.36-40
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• 2013

A novel design method of ultra wideband bandpass filter using CRLH transmission line with Dumbell type DGS is presented in this paper. Defected Ground Structure and microstrip interdigital capacitor are used to design the ultra wideband (UWB) filter. CRLH transmission line has composite characteristics of low pass and high pass filter. As control of cutoff frequency of low pass and high pass response on CRLH transmission line, we can get characteristic of UWB filter. We designed and simulated for CRLH transmission lines with one, two, four, and eight cells. A UWB filter using four cells CRLH is designed and fabricated to verify the results. The characteristics of designed filter have center frequency of 5GHz and relative bandwidth of 88%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• The KIPS Transactions:PartA
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• v.19A no.3
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• pp.113-120
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• 2012

The visibility for signals in designs is required for their analysis and debug during the verification process. It could be achieved through the signal dumping for designs during the execution of HDL simulation. However, such signal dumping, in general, degrades the speed of simulation significantly, or can result in the number of simulation runs. In this paper, we have proposed an efficient and fast simulation method for dumping based on the design checkpoint, and shown its effectiveness by applying it to industrial SOC designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Journal of Broadcast Engineering
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• v.8 no.4
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• pp.410-426
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• 2003

MPEG-21 defines a digital item as an atomic unit lot creation, delivery and consumption in order to provide an integrated multimedia framework in networked environments. It is expected that MPEG-21 standardization makes it Possible for users to universally access user's preferred contents in their own way they want. In order to achieve this goal, MPEG-21 has standardized the specifications for the Digital Item Declaration (DID). Digital Identification (DII), Rights Expression Language (REL), Right Data Dictionary (RDD) and Digital Item Adaptation (DIA), and is standardizing the specifications for the Digital Item Processing (DIP), Persistent Association Technology (PAT) and Intellectual Property Management and Protection (IPMP) tot transparent and secured usage of multimedia. In this paper, we design an MPEG-21 terminal architecture based one the MPEG-21 standard with DID, DIA and DIP, and implement with the MPEG-21 terminal. We make a video summarization service scenario in order to validate ow proposed MPEG-21 terminal for the feasibility to of DID, DIA and DIP. Then we present a series of experimental results that digital items are processed as a specific form after adaptation fit for the characteristics of MPEG-21 terminal and are consumed with interoperability based on a PC and a PDA platform. It is believed that this paper has n important significance in the sense that we, for the first time, implement an MPEG-21 terminal which allows for a video summarization service application in an interoperable way for digital item adaptation and processing nth experimental results.

• Journal of Digital Convergence
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• v.12 no.8
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• pp.493-499
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• 2014

This study aims to verify the effects of the life redesign educational program based on the baby boomer (11 members of experimental group, 12 members of control group). The program was conducted for two hours two times in a week in the area of Chungnam (Total 8weeks 16sessions). First, in the result of the Wilcoxon's pairs signed-ranks test between the pre-post tests for the analysis on the program effectiveness of the experimental group of baby boomer, the baby boomer of experimental group showed an improved perception of preparing the volunteer work in the perception of preparing their old age, and there was no pre-post significant differences in the control group. In case of the experimental group, perception of the post-retirement preparation, such as a physical preparation, emotional preparation, financial preparation, volunteer work preparation and leisure activities preparation increased in average. Second, the satisfaction for the program's educational process, educational contents, educational data, educational method, instructor and the educational environment were shown to be more than 3.5 points out of 5 points in full.

• Journal of IKEEE
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• v.14 no.3
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• pp.190-198
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• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].