The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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Simulation Method based on Design Checkpoint for Efficient Debugging

효율적 디버깅을 위한 디자인 체크포인트 기반 시뮬레이션 방법

  • 심규호 (삼성전자 System LSI 사업부) ;
  • 김남도 (삼성전자 System LSI 사업부) ;
  • 박인학 ((주)시스템센트로이드) ;
  • 민병언 (삼성전자 System LSI 사업부) ;
  • 양세양 (부산대학교 컴퓨터공학과)
  • Received : 2012.03.28
  • Accepted : 2012.05.12
  • Published : 2012.06.30
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Abstract

The visibility for signals in designs is required for their analysis and debug during the verification process. It could be achieved through the signal dumping for designs during the execution of HDL simulation. However, such signal dumping, in general, degrades the speed of simulation significantly, or can result in the number of simulation runs. In this paper, we have proposed an efficient and fast simulation method for dumping based on the design checkpoint, and shown its effectiveness by applying it to industrial SOC designs.

디지털시스템 설계에 대한 HDL 시뮬레이션을 통한 검증 과정에서는 설계에 대한 분석 및 디버깅을 위하여 설계에 존재하는 수많은 신호선들에 대하여 시뮬레이션 실행 중에 시그널 덤핑을 통한 가시도 확보가 필요하게 된다. 그러나 이와 같은 시그널 덤핑은 일반적으로 시뮬레이션의 속도를 크게 떨어뜨리는 문제점을 가지고 있거나, 시뮬레이션의 실행 횟수를 늘리는 문제점을 초래한다. 본 논문에서는 디자인 체크포인트를 활용하여서 시그널 덤핑을 효율적이며 신속하게 수행하는 시뮬레이션 방법을 제시하고, 이를 시스템반도체급의 대규모 회로인 산업체 설계들에 적용하여 제안된 방법이 효과적임을 확인하였다.

Keywords

References

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