• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.4
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• pp.569-574
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• 2007

최근 많은 광대역 유무선 통신 응용분야에서 OFDM(Orthogonal Frequency Division Multiplexing) 방식을 표준기술로 채택하고 있다. OFDM 방식의 고속 무선 데이터 통신을 위한 FFT 프로세서는 일반적으로 DSP(Digital Signal Processing)로 구현되었으나, 큰 전력 소비를 필요로 한다. 따라서, OFDM 통신방식의 단점인 전력문제를 보완하기 위해서 전류모드 FFT LSI가 제안되었고, 저소비전력 전류모드 FFT LSI를 동작시키기 위해서는 전류모드를 전압모드로 바꾸는 VIC(Voltage to Current Converter) 그리고 다시 전류모드를 전압모드로 바꾸어 주는 IVC(Current to Voltage Converter)가 필요하다. 그러나, OP-AMP로 구현되는 종래의 IVC는 회로규모가 크고, 전력소비가 크며, LSI 내에 크고 정확한 높은 저항을 필요로 한다. 또한 전류모드신호처리에서 많이 이용되는 Current Mirror 회로 등의 출력단자로부터 전류신호를 입력받은 경우, 입력단자간의 전위차가 발생하며, DC offset 전류가 발생하는 등의 문제점을 갖는다. 따라서 본 연구에서는 저전력 동작이 가능하고, 향후, single chip 응용이 가능한 IVC를 $0.35{\mu}m$ 공정에서 설계함으로서, $0.35{\mu}m$ 공정에서의 전류모드 FFT LSI의 전압모드 출력이 가능해졌다 설계된 IVC는 FFT LSI의 출력이 디지털신호로 환산한 ${\pm}1$인 점을 감안하여, 전류모드 FFT LSI의 출력이 $13.65{\mu}A$ 이상일 때에 3.0V의 전압을 출력하고, FFT LSI의 출력이 $0.15{\mu}A$ 이하일 때에 0.5V 이하의 전압을 출력하도록 하였으며, IVC의 총 소비전력은 약 1.65mV이하로 평가되었다.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of IKEEE
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• v.17 no.4
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• pp.511-516
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• 2013

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.36-43
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• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.4
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• pp.229-240
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• 2006

The advanced Alarm System (AS) employs modem digital technology to implement the alarm functions of the NPP(Nuclear Power Plant). The use of modem digital technology can provide advanced alarm processing in which new algorithms such as a signal validation, advanced alarm processing logic and other features are applied to improve the control room man-machine interfaces. This paper will describe the design process of the AS of NPP, improving the system reliability and availability using the reliability prediction tool, design strategies regarding the human performance topics associated with a computer-based AS and the results of the performance analysis using a prototype of the AS.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.31-36
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• 1998

In this paper, Image Rejection Interdigital Filter(IRIF) for 5.8GHz wireless LAN was designed and implemented. When the input signal is -30dBm in the 4~8㎓ frequency band, the insertion loss including all kinds of loss is 6.3dB in the center frequency 5.775GHz. Therefore, it was showed practically insertion loss of about -3.3dB. Especially, image signal rejection is about -l7dB in the image frequency 6.475GHz. and skirt characteristics of the high frequency band is very excellent. Therefore, it was confirmed that the proposed IRIF is suitable for RF image signal rejection in the 5.8GHz wireless LAN system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.283-296
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• 2004

TV-Anytime metadata can be delivered by unidirectional or bi-directional network. In bi -directional environment, the special request of a client is sent to metadata service providers and then the providers provide the personalized metadata back to the client. In this paper. we introduce the design and implementation of a broadcasting receiver for personalized broadcasting service in bi-directional environment. We describe actual system configuration and usage examples for bi-directional personalized service. The implemented receiver provides various functions for a digital broadcasting recorder and is based on TV-Anytime specification and UDDI specification to provide the metadata service discovery.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.796-799
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• 2008

최근 유비쿼터스 컴퓨팅과 유비쿼터스 네트워크를 활용하여 새로운 서비스들을 개발하려는 노력이 진행 중이며, 이와 관련된 기술의 중요성도 급증하고 있다. 특히 감시정찰 센서네트워크의 핵심 구성요소인 저가의 경량 센서노드에서 측정한 미가공 데이터(raw data)를 사용하여 침입 물체의 실시간 탐지, 식별, 추적 및 예측하기 위한 디지털 신호처리 기술은 주요 기술 중 하나이다. 본 논문에서는 감시정찰 센서네트워크의 핵심 구성요소인 소리센서 노드에서 측정한 소리 미가공 데이터를 사용하여 차량을 탐지할 수 있는 소리센서 디지털 신호처리 알고리즘을 설계 및 구현 한다. 알고리즘의 주 목표는 감시정찰용 센서노드의 탐지 신뢰성을 높이기 위한 높은 침입물체 탐지 성공률(success rate)과 낮은 허위신고(false alarm) 횟수를 가지는 것이다. 성능평가 결과에 의하면 제안한 AMIDA 알고리즘은 90% 이상의 탐지 성공률과 2 회 이하의 허위신고 횟수를 가지는 것을 확인할 수 있었다.