• Defense and Technology
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• no.3 s.145
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• pp.17-25
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• 1991

Sting Ray는 현대의 첨단기술로 제작된 경어뢰로서, 완전히 디지털 컴퓨터 제어에 의해 작동한다. 항공기에 장착된 유도미사일과 그 기능을 견줄수 있는 최첨단 수중유도무기이며, 수중에서의 음파탐지 및 식별에 수반되는 각종 난관을 극복하였다. 수중에서의 음의 반사 및 굴절효과로 인해 복잡성이 가중된 잡음의 근원과 바닷물의 특성이 수시로 변화되는 상황에서 음향장치 사용을 결정하는 것은 매우 어려운 과제이나, Sting Ray는 이러한 어려운 환경을 극복할수 있도록 설계되었다. 또한 선박, 항공기 또는 헬기등 어디에서 발사되더라도 자율적으로 자체의 전술을 창조하는 Shaped Charge형 탄두는 어떠한 표적에도 치명적 피해를 줄수 있다

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.219-222
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• 1987

A Semi-cusion VLSI Digital Filter Design for TDM/FDM tran-smultiplexer is decribed. Using the polyphase network approach a filter bank composed of only all-pasdigital filter sections was designed. The use of all-pass filters as basic building blocks is shown to provide a Transmultiplexer structure that has low computational requirements low quanization noise and hign modularity. A design of 1st order 2nd All pass filter is done using COMS 2um double metal.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.590-596
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• 1987

In this paper, it was studied on the design of a sun sensor which is able to sense the declinations of an azimuth angle and a zenith angle for a digital sun seeker control system so that it will seek the sun accurately. And, it was considered the construction of digital controllable algorithms through experiments. Peculiar design method of the sun sensor is that sensor box was constructed with three square silicon solar cells and that the three cells were mounted unsymmetrical forming the

• Optical Science and Technology
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• v.8 no.2
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• pp.14-21
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• 2004

캠코더, 빔 프로젝터, 대형 프로젝션 TV, CD-ROM 드라이버, DVD Player, 레이저 프린터 등의 많은 광학 제품들이 대중화되어 일반 소비자에게 널리 판매되고 있다. 제품 및 서비스의 디지털화에 부합하여 이들 광학 제품의 시장 규모와 중요성은 점점 커지고 있다. 본 기사에서는 최근 광학제품의 핵심부품으로서 널리 이용되고 있는 비구면 렌즈의 제조 과정에서 CAD/CAM 응용기술이 어떻게 활용될 수 있는 지를 살펴보고자 한다. CAD/CAM이란 Computer Aided Design과 Computer-Aided Manufacturing의 약어로써 제품의 설계와 제조 과정에서 컴퓨터를 활용하는 기술을 의미한다.(중략)

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.229-233
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• 2003

오늘날 많은 양의 데이터가 디지털 논리 회로와 상호 연결에 의해서 다양한 컴퓨터 시스템과 서브시스템 사이에서 전송된다. 데이터가 전송될 때 전자적 잡음, 장치 결함, 시간 오류 등에 의해서 오류가 발생한다. 일반적으로 비트 오류가 발생했을 때 패리티 검사회로가 사용된다. 시스템의 신뢰성과 유용성을 높이기 위해서는 효율적인 패리티 검사회로가 요구된다. 본 논문에서는 PBCA의 특성행렬을 이용하여 거리가 3인 부호를 생성하는 방법과 오류 정정에 사용되는 행렬을 구성하는 방법 및 복호기법을 제시한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.33-43
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• 2000

The guarantee of the fast dynamics stability is essential for successful application of singular Perturbation technique to control systems design. Even though the fast dynamics of the control systems is rendered stable by an analog controller, the fast dynamics stability of the control systems resulted from an digital implementation of the analog controller can be impaired severely. In this paper, we first investigate the time sampling effects on singular perturbation based control systems by centering on a design example of recently developed singular perturbation based STT missile autopilot with high performance. The investigation shows that the stability margin the fast dynamics of the STT misile autopilot system decreases rapidly as the sampling interval of discretizing the analog autopilot increases. Under this analysis, we propose a composite digital controller with compensation for the decreasing stability margin of the fast dynamics due to time sampling to achieve better performance with respect to sampling time. The improved performance of the proposed composite digital controller is verified by simulation. This result shows that one needs to investigate time sampling effects in the digital implementation of singular perturbation based controllder, and then can have benefit from the investigation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5427-5433
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• 2012

In this paper a ultrasonic level meter for accurately and simply measuring oil levels of vehicle transmission is developed and its effectiveness is shown by experiments. By using a FPGA, all digital signal processes for the oil level calculation is fulfilled, and the programming on a FPGA project IDE enables very short developing time. And besides, analog circuits including a transmit/receive switch, multi-stage active filters and an envelope detect circuit are designed to process low-level ultrasonic echo signal. Under experiments, the designed level meter has proven to have the accuracy of about within 1[mm] scale.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.138-144
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• 2013

In XRF systems, various techniques have been developed for the synthesis of pulse shapes using digital methods instead of traditional analog methods. Trapezoidal pulse shaping algorithms can be used for digital multi-channel pulse height analysis in X-ray spectrometer systems. In this paper, an efficient trapezoidal filter architecture is presented. In addition, we present a hardware-efficient peak value detection algorithm. By the proposed algorithm, peak value detection error is decreased by half compared with the conventional algorithm. The proposed Digital Pulse Processing(DPP) algorithm is designed using Verilog HDL and implemented using an FPGA on a test board. It is demonstrated that the implemented DPP board works successfully in practical XRF systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1074-1079
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• 1999

A high performance CMOS receiver for 155.52 Mbps STM-1 digital communication has been designed and fabricated. The ASIC operates properly with 155.52 MHz clock frequency in case of the data loss due to some system error such as transmission line open or data transfer fail. Also it operates properly in case the system starts after the power failure or system maintenance. The designed circuit has especially PLL based self oscillation loop which operates on abnormal environment which is added to main oscillation loop. The measured results show that the circuit operates well with 153.52 MHz clock frequency not only on normal environment but also on abnormal environment. Rms jitter of the PLL loop is about 23 ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.67-74
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• 2004

In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track ＆ Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.