• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2634-2636
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• 2004

다목적실용위성2호의 위성 본체시스템에는 지상과 연락을 담당하는 주 컴퓨터인 OBC, 위성의 자세를 제어를 위한 원격구동장치인 RDU 그리고 위성의 전원분배를 제어장치인 ECU인 3개의 동일 프로세서(386)가 탑재되어 각 담당 임무를 수행하는 분산형 구조를 갖고 있다. 각 프로세서는 EEPROM과 SRAM 데이터 메모리를 갖고 있는데 전원 리셋이 일어나면 모든 프로그램은 EEPROM에서 SRAM으로 복사되어 운영 프로그램이 실행하도록 되어 있다. 그러나 SRAM은 우주환경에서 위성체는 방사선에 노출되어 손상을 입을 때 SEU이 발생되어 정보가 왜곡되거나 상실되는 문제를 갖고 있다. 그러므로 본 논문에서는 변형된 해밍코드 기법을 이용하여 데이터를 수신하는 곳에서 에러를 검출 및 수정하는 디지털 회로 설계방법을 기술하고자 한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.137-144
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• 1990

We describe how single layer perceptrons and new nonsymmetry feedback type neural networks can be implemented by VLSI CMOS technology. The network described provides a flexible tool for evaluation of boolean expressions and arithmetic equations. About 50 CMOS VLSI chips with an architecture based on two neural networks have been designed and me being fabricated by 2-micrometer double metal design rules. These chips have been developed to study the potential of neural network models for the use in character recognition and for a neural compute.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.818-823
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• 2003

본 논문에서는 입력 매칭(input matching) BIST(Built-In Self-Test) 회로를 이용한 RF font end의 새로운 결함 검사방법을 제안한다. BIST 회로를 가진 RF front end는 1.8GHz LNA(Low Noise Amplifier: 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 0.25$\mu\textrm{m}$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함 및 parametric 변동을 가진 RF front end와 결함을 갖지 않은 RF front end를 판별하기 위해 RF front end의 입력 전압 특성을 조사하였다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전자계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 RF front end가 차지하는 전체면적의 약 10%에 불과하다. 본 논문에서 제안하는 검사기술을 이용하여 시뮬레이션해 본 결과 catastrophic 결함에 대해서는 100%, parametric 변동에 대해서는 약 79%의 결함을 검출할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.194-200
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• 2003

In this paper, FSK(Frequency Shift Keying) demodulator which is widely used for FH-SS system is designed and the experimental results are analyzed. The performance of the ADPLL(All-digital Phase-Locked-Loop), which is the main part of the demodulator circuit, is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the ADPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. There is about 2${\mu}\textrm{s}$ difference in time constant of the PLL. This difference is not critical in the demodulator. And the experimental results show that the transmitted data is well demodulated when the phase difference between the FSK modulated signal and the reference signal is about 180 degree.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.106-113
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• 1997

A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.

• Journal of IKEEE
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• v.24 no.3
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• pp.719-726
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• 2020

A threshold-voltage sensing circuit is proposed to compensate for pixel aging in active matrix organic light-emitting diodes. The proposed threshold-voltage sensing circuit consists of sample-hold (S/H) circuits and a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 10 bits. To remove a scale down converter of each S/H circuit and a voltage gain amplifier with a signl-to-differentail converter, the middle reference voltage calibration and input range calibration for the single-ended SAR ADC are performed in the capacitor digital-to-analog converter and reference driver. The proposed threshold-voltage sensing circuit is designed by using a 180-nm CMOS process with a supply voltage of 1.8 V. The ENOB and power consimption of the single-ended SAR ADC are 9.425 bit and 2.83 mW, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.101-104
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• 2016

In this study, we propose an algorithm to simulate the function of the coupling structure and having two neurons to find out exactly recover the temporary or permanent position errors that can occur during operation in a digital circuit was separated by function, a 3x3 array. If any particular part in the combined cells are differentiated cells have a problem that function to other cells caused an error and perform the same function are subjected to a step of apoptosis by the surrounding cells. Designed as a function block in the function and the internal structure having a cell structure of this digital circuit proposes an algorithm.

• Bulletin of the Korean Space Science Society
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• 2010.04a
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• pp.37.5-38
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• 2010

경희대학교 우주탐사학과에서는 우주공간 탐사를 위해 Trio(TRiplet Ionospheric Observatory)-CINEMA(Cubesat for Ions, Neutrals, Electrons and MAgnetic fields)로 명명된 초소형 위성을 개발하고 있다. 과학임무는 지구 저궤도에서 고에너지 입자를 관측하는 것이며, 이를 위해 고에너지 (2~300keV) 입자 검출기와 자기장 측정기가 탑재된다. 저에너지 입자 검출기 시스템인 STEIN(SupraThermal Electrons, Ions, Neutrals)은 $1\times4$ Array의 개선된 실리콘 검출기와 이온, 전자, 중성입자를 분리할 수 있는 정전장 편향기, 그리고 신호를 처리하는 전자회로로 구성되어있다. 설계된 전자회로는 매우 작은 검출기 기판, 아날로그 기판과 디지털 기판으로 이루어져 있고, 475mW 이하의 저 전력으로 동작한다. 또한 2~100keV의 에너지를 1keV이하의 해상도로 30,000event/sec/pixel 까지 관측 할 수 있도록 회로를 설계하였다. 센서로 들어온 입자로 인해 발생한 펄스의 신호는 4개의 아날로그 회로가 담당하게 되는데, Folded cascode amplifier를 배치하여 증폭률을 높인 Charge sensitive amplifier를 통해 신호를 증폭하고, $2{\mu}s$ unipolar gaussian shaping amplifier를 통해 읽기 쉽게 처리된 신호를 상한파고선별기와 하한파고 선별기를 통해 유효 값 여부를 판단하고, 피크 검출기를 통해 피크의 타이밍을 측정한 뒤 신호를 아날로그-디지털 변환 회로를 통하여 8bit의 값으로 나타내어, 입자들의 Spectrum을 측정하게 된다. 크기와 소비전력이 적음에도 검출성능이 우수하기 때문에 이 시스템은 향후 우주탐사 시스템에 있어 매우 중요한 역할을 수행 할 것으로 생각한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.857-867
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• 2018

Active array radar is evolving into digital active array radar. Digital active array radar has many advantages for making several simultaneous radar beams from the digital receive data of each element. A digital-type transceiver(TR) module is suitable for this goal in radar. In this work, the design results of an L-band digital TR module are presented to verify the possibility of fabrication for a digital active array antenna. This L-band digital TR module consists of a gallium-nitride-type HPA to achieve a more than 350-W peak output power and one-chip transceivers that include a digital waveform generator and analog digital converter. The receiving gain was 47 dB, the noise figure was less than 2 dB, and the final output type of the four channel receiving paths was one optic signal.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.