• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.4
• /
• pp.1903-1907
• /
• 2013

Heart condition should be observed for long periods of time because it does not appear abnormal all the time. However, there are many difficulties checking our health for a long time due to its size, operation of equipment, and cost. To solve these problems, an electrocardiograms(ECG), specially interfacing three gel-less metal electrodes for low cost portable applications, is designed and implemented. Gel-less metal electrodes are used for ECG monitoring system instead of gel-type electrodes that can cause skin rashes and itching problem. The whole ECG system consists of two parts-analog and digital circuits. The analog measurement circuit that has a 18*25mm size is made up of op-amps maintaining a sufficiently high common-mode noise rejection and passive elements of SMD type. Analog heart signal is converted to digital stream suitable for display on a TFT-LCD by an 8-bit microcontroller. The size of the completed ECG system is 25*80*50mm and its weighing is about 150g, which is small enough to be easily used. Therefore, the implemented ECG system can be used as a portable one.

• Journal of Korea Society of Industrial Information Systems
• /
• v.19 no.1
• /
• pp.61-67
• /
• 2014

Conventional synchronous circuits in low power required systems such as sensor systems cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in the reliable ultra-low power design, asynchronous circuits have recently been reconsidered as a solution for scaling issues. However, it is not easy to totally replace synchronous circuits with asynchronous circuits in the digital systems, so the interfacing between the synchronous and asynchronous circuits is indispensable for the digital systems. This paper presents a new design for interfacing between asynchronous circuits and synchronous circuits, and the interface circuits are applied to a $4{\times}4$ multiplier logic designed using 0.11um technology.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.2
• /
• pp.112-118
• /
• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.10 no.6
• /
• pp.900-909
• /
• 1999

The receiving part of the RF system for the digital TRS base stations is developed in this paper. Based on the system specifications, the structure of the RF system is accomplished and its block diagram is drawn. The RF system is implemented according to these block diagrams. Subsequently the RF band-pass filter, the low noise amplifier, the automatic level controlled attenuator, the frequency synthesizer and other components for the system are designed and implemented, and a main board to integrate these modules is also manufactured. To lower the noise floor of the system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the RF system and the entire system, the performance tests are accomplished to check the specifications.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.5C
• /
• pp.378-385
• /
• 2008

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a $0.25{\mu}m$ pure digital CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.354-356
• /
• 2013

본 논문에서는 CMOS 스위치를 이용한 디지털 이득 제어 구조를 가진 이득 조절 증폭기 (PGA, Programmable Gain Amplifier)를 제안한다. 기존의 아날로그 이득 제어 방식에서는 가변적인 트랜스 컨덕턴스를 활용하는 과정에서 바이어스 전류나 전압에 의해 이득이 변하게 되어 순간적으로 구성회로의 바이어스 포인트가 변하기 때문에 왜곡이 발생하게 되는 문제점이 있다. 본 논문에서는 이러한 문제점을 해결하기 위해 기존의 gm-boosting 증폭기를 변형한 디지털 이득 제어 방식으로 설계되어 있기 때문에 우수한 선형성을 가지며 특수 목적에 맞도록 그 이득을 6dB에서 60dB까지 7가지 단계로 조절 가능하다. 제안한 PGA는 기존 회로에 비해 0.2dB 보다 작은 이득오차와 0.47mW의 낮은 소비전력 특성을 보였다.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.51-58
• /
• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.12A
• /
• pp.1311-1319
• /
• 2007

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.10
• /
• pp.917-925
• /
• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.2
• /
• pp.330-336
• /
• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has tern designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.