• Title/Summary/Keyword: 디지털수신기

Search Result 345, Processing Time 0.031 seconds

Development of the S-band receiver for LEO satellite (저궤도 위성용 S대역 수신기의 개발)

  • Park, In-Yong;Jin, Hyun-Peel;Lee, Soon-Cheon;Sirl, Young-wook
    • Journal of the Korean Society for Aeronautical & Space Sciences
    • /
    • v.44 no.3
    • /
    • pp.212-217
    • /
    • 2016
  • The S-band receiver for Low Earth Orbit satellite is designed and fabricated as engineering model. Demodulator is implemented by using FPGA for extension of demodulator method. The receiver consists of RF Block, Digital demodulator and Power stage and has a Doppler tracking function to compensate a frequency shift that occur on the operation. The measured results of fabricated receiver show BER of less than $1.0{\times}10^{-6}$ at -110dBm RF input power and equipped a frequency tracking of ${\pm}100KHz$ relative to the center frequency. TID test was satisfied with the results of the test criterion is 10krad.

FPGA Implementation of a BFSK Receiver for Space Communication Using CORDIC Algorithm (CORDIC 알고리즘을 이용한 우주 통신용 BFSK 수신기의 FPGA 구현)

  • Ha, Jeong-Woo;Lee, Mi-Jin;Hur, Yong-Won;Yoon, Mi-Kyung;Byon, Kun-Sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2007.06a
    • /
    • pp.179-183
    • /
    • 2007
  • This paper is to implement a low power frequency Shift Keying(FSK) receiver using Xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

  • PDF

The Design of Multi Channel Receiver for Radar Systems (레이더용 다중채널수신기 설계)

  • Lee, Ki-Hong;Kim, Wan-Sik;Kim, Gye-Kuk
    • Proceedings of the Korean Society of Computer Information Conference
    • /
    • 2010.07a
    • /
    • pp.203-207
    • /
    • 2010
  • In this paper, The design and implementation of Multi Channel Receiver is described in this paper. This Receiver system operates at X-band with processing received signal, more than 80[dB] dynamic range and wide-band signals at the same time. To process direct received signals, this system has the built-in Digital De-modulators which offer the minimum loss on the receiving signal pass and has high stability by adding Built-In Test (BIT). The performance of Multi Receiver is the following. The gain, noise figure, difference of amplitude and phase on the signal pass is respectively $14{\pm}2[dB]$, 19[dB], ${\pm}2[dB]$, and $10^{\circ}$ below.

  • PDF

Mobile Performance Evaluation of ISDB-T Full-Segment TV Receiver (ISDB-T 풀세그 TV 수신기 이동 성능 평가)

  • Gu, Young Mo
    • Journal of Broadcast Engineering
    • /
    • v.23 no.2
    • /
    • pp.293-301
    • /
    • 2018
  • In ISDB-T, which is Japanese digital terrestrial TV specification based on OFDM technology, 6MHz bandwidth is divided into 13 segments. Twelve segments (full-seg) are used for high definition broadcasting for fixed receivers and one segment (one-seg) for mobile receivers. Though one-seg supports high speed mobility by using QPSK modulation, it is not suitable for large display mobile devices because of its low data rate. Full-seg using 64QAM modulation also suffers from its low mobile performance. In this paper, mobile performance of ISDB-T full-seg receiver is evaluated by applying sub-carrier interference removing scheme, high speed mobile channel estimation scheme and antenna diversity scheme.

The Implementation of DDC for the WLAN Receiver (WLAN 수신기를 위한 Digital Down Converter (DDC) 구현)

  • Jeong, Kil-Hyun
    • Journal of the Korea Society of Computer and Information
    • /
    • v.17 no.2
    • /
    • pp.113-118
    • /
    • 2012
  • In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

Design of RF Front-end for High Precision GNSS Receiver (고정밀 위성항법 수신기용 RF 수신단 설계)

  • Chang, Dong-Pil;Yom, In-Bok;Lee, Sang-Uk
    • Journal of Satellite, Information and Communications
    • /
    • v.2 no.2
    • /
    • pp.64-68
    • /
    • 2007
  • This paper describes the development of RF front.end equipment of a wide band high precision satellite navigation receiver to be able to receive the currently available GPS navigation signal and the GALILEO navigation signal to be developed in Europe in the near future. The wide band satellite navigation receiver with high precision performance is composed of L - band antenna, RF/IF converters for multi - band navigation signals, and high performance baseband processor. The L - band satellite navigation antenna is able to be received the signals in the range from 1.1 GHz to 1.6 GHz and from the navigation satellite positioned near the horizon. The navigation signal of GALILEO navigation satellite consists of L1, E5, and E6 band with signal bandwidth more than 20 MHz which is wider than GPS signal. Due to the wide band navigation signal, the IF frequency and signal processing speed should be increased. The RF/IF converter has been designed with the single stage downconversion structure, and the IF frequency of 140 MHz has been derived from considering the maximum signal bandwidth and the sampling frequency of 112 MHz to be used in ADC circuit. The final output of RF/IF converter is a digital IF signal which is generated from signal processing of the AD converter from the IF signal. The developed RF front - end has the C/N0 performance over 40dB - Hz for the - 130dBm input signal power and includes the automatic gain control circuits to provide the dynamic range over 40dB.

  • PDF

A Study On The Introduction Of The Digital Radio And Frequency Utilization (디지털라디오 도입과 주파수 활용에 관한 연구)

  • Park, Sung-Kyu;Park, Goo-Man
    • Proceedings of the Korean Society of Broadcast Engineers Conference
    • /
    • 2013.06a
    • /
    • pp.344-347
    • /
    • 2013
  • 본 고에서는 AM과 FM라디오의 디지털방송 전환을 위하여 현재 사용 중인 방송대역에서의 IN-BAND 방식 외에도 VHF 하위대역 혹은 VHF상위대역을 사용하는 OUT-Of-BAND 방식에 대해 각 전송방식의 장단점을 분석하였다. 그러나 현재 디지털라디오뿐만 아니라 TV도 UHDTV 도입을 위해 VHF상위대역 주파수 사용을 원하고 있어 DMB와 라디오와 TV의 차세대방송 주파수 요구가 상호 충돌이 예상된다. 그러므로 본 고에서는 FM의 디지털라디오 전환방법으로 VHF하위대역(TV채널 5번과 6번)에서의 OUT-Of-BAND 방법에 의한 DRM+ 전송방식 적용을 제안하고 있다, 중파라디오의 디지털방송도 동일 계열 DRM 기술 적용으로 수신기를 값싸게 제조하고 빠르게 보급함으로써 디지털라디오의 활성화 방안을 제시하고 있다.

  • PDF

Implementation of European Digital Radio Analyzer for In-Band Frequency (유럽형 In-Band 디지털 라디오 분석기 구현)

  • Kim, Seong-Jun;Kwon, Ki-Won;Park, Kyung-Won;Lee, Min-Soo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
    • /
    • 2011.11a
    • /
    • pp.23-24
    • /
    • 2011
  • 아날로그 TV의 디지털화와 마찬가지로 아날로그 라디오 방송의 디지털화도 세계적인 추세이다. DRM(Digital Radio Mondiale)은 송신소의 위치, 방송 지역 및 사용하는 주파수에 따라, 동작모드가 A~E까지 5가지가 있으며, 모드 A~D는 30MHz이하 대역의 디지털 라디오 방송에 사용되는 모드이며, 모드 E는 Band I~II 대역의 디지털 라디오 방송에 사용되는 모드이다. 본 논문에서는 DRM 모드 A~E까지의 신호를 수신 및 분석 가능한 USB 타입 DRM 수신기 구현에 관하여 정리하였다. 대역 필터 및 디지털 다운 컨버터가 DSP를 이용하여 구현되었으며 PC Side에서 DRM 신호를 분석할 수 있도록 설계되었다.

  • PDF

Design of Digital Signal Processor for Ethernet Receiver Using TP Cable (TP 케이블을 이용하는 이더넷 수신기를 위한 디지털 신호 처리부 설계)

  • Hong, Ju-Hyung;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.32 no.8A
    • /
    • pp.785-793
    • /
    • 2007
  • This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

Classification of Program Information Genre for Intelligent Personalized EPG (지능형 개인화 EPG를 위한 프로그램 정보 장르 분류)

  • Song, Jin-Seok
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2007.05a
    • /
    • pp.435-438
    • /
    • 2007
  • 국내에서 디지털 방송 상용화에 성공하고 전송 모델 또한 다양화됨에 따라 사용자는 다양한 형식으로 다수의 방송 프로그램을 접할 수 있게 되었다. 이에 대한 효율적인 프로그램 관리를 위한 EPG(Electronic Program Guide) 서비스가 현재 제공되거나 개발 중이다. 지능형 개인화 EPG는 디지털 방송 스트림이 수신되는 환경에서 사용자와 방송 수신기의 지능적인 매개체로서 운영되며 본 연구는 기존 프로그램 정보에 대한 장르를 학습하고 새로운 프로그램 정보가 입력될 경우 올바르게 장르를 분류할 수 있도록 기계학습 기법이 사용되었다.

  • PDF