• Title/Summary/Keyword: 디지털변환처리

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A Study on Watermarking Digital Images for Copyright Protection (디지털 영상의 저작권 보호를 위한 워터마킹에 관한 연구)

  • 배익성;김강석;차의영
    • Proceedings of the Korean Information Science Society Conference
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    • 1998.10c
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    • pp.577-579
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    • 1998
  • 본 논문에서는 디지털 영상 데이터에 워터마크를 삽입하는 알고리즘을 제시한다. 디지털 데이터를 주파수 공간으로 변환시켜 인간이 잘 감지 못하는 주파수 영역과 중요한 주파수를 선택하여 대역확산통신(Spread Spectrum Communication)에서 사용되는 유사한 방법으로 워터마크를 삽입하였다. Fourier 스펙트럼 공간에서 JPEG 압축의 다양한 양자화 단계를 거쳐도 변화가 덜 민감한 Phase에서 워터마크를 삽입할 주파수 영역을 찾았다. 원본과 워터마크가 삽입된 데이터를 가지고 워터마크는 자기상관관계 특성으로 추출하였다. 그리고 다양한 신호처리(손실 압축, 필터링, 양자화)에도 워터마크를 추출하였다.

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The development of digital camera for the medical DF instrument (의료용 DF 장비의 디지털 카메라 개발)

  • 김용민;이성운;구기현;김진용;김승식;문지영
    • Proceedings of the Optical Society of Korea Conference
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    • 2003.07a
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    • pp.76-77
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    • 2003
  • Digital Radiograpy & Fluoroscopy(DRF 또는 DR 또는 DF)는 cone beam을 이용하여 인체를 투과한 X선을 영상증배관(Image Intensifying Tube: IIT)을 통하여 가시광선으로 변환시킨 후 영상을 카메라로 보내고, 이곳에서 발생한 영상정보를 디지털로 처리하여 모니터를 통해 눈에 보이는 영상으로 만드는 방법으로 IIT에 기초한 디지털 방사선 촬영술이라고도 한다. DF 방법은 즉시 영상 표시와 진단이 가능하기 때문에 즉시성이 요구되는 심장이나 두복부 등의 순환기 분야에서 DSA(Digital Subtraction Angiography) 장비로 이용되고 있고, 순환기뿐만 아니라 위를 중심으로 한 소화관(식도, 위, 소장, 대장, 직장)의 분야에서 적용 가능하다. (중략)

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Random Partial Haar Wavelet Transformation for Single Instruction Multiple Threads (단일 명령 다중 스레드 병렬 플랫폼을 위한 무작위 부분적 Haar 웨이블릿 변환)

  • Park, Taejung
    • Journal of Digital Contents Society
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    • v.16 no.5
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    • pp.805-813
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    • 2015
  • Many researchers expect the compressive sensing and sparse recovery problem can overcome the limitation of conventional digital techniques. However, these new approaches require to solve the l1 norm optimization problems when it comes to signal reconstruction. In the signal reconstruction process, the transform computation by multiplication of a random matrix and a vector consumes considerable computing power. To address this issue, parallel processing is applied to the optimization problems. In particular, due to huge size of original signal, it is hard to store the random matrix directly in memory, which makes one need to design a procedural approach in handling the random matrix. This paper presents a new parallel algorithm to calculate random partial Haar wavelet transform based on Single Instruction Multiple Threads (SIMT) platform.

Construction of the Multiple Processing Unit by De Bruijn Graph (De Bruijn 그래프에 의한 다중처리기 구성)

  • Park, Chun-Myoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.12
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    • pp.2187-2192
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    • 2006
  • This paper presents a method of constructing the universal multiple processing element unit(UMPEU) by De Bruijn Graph. The second method is as following. First, we propose transformation operators in order to construct the De Bruijn UMPEU using properties of graph. Second, we construct the transformation table of De Bruijn graph using above transformation operators. Finally we construct the De Bruijn graph using transformation table. The proposed UMPEU be able to construct the De Bruijn graph for any prime number and integer value of finite fields. Also the UMPEU is applied to fault-tolerant computing system, pipeline class. parallel processing network, switching function and its circuits.

Gray-level Image Watermarking using Wavelet Transform (웨이브렛 변환을 이용한 그레이-레벨 영상 워터마킹)

  • Min, Sun-Jin;Chung, Hoon;Kim, Chung-Hwa
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.10a
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    • pp.487-490
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    • 2001
  • With the establishment of the optimized copyright, digital image watermarking technique is demended to identify the owner of a certain image and to avoid the unauthorized distribution of digital image copies. Also, a robust watermarking approach should survive several possible attacks, such as image processing and lossy image compession. The proposed scheme distributes the 256 gray-level signature information in discrete wavelet transform domain of the host image where is very little visible distortion. While much of the privious work used signature data that is a small fraction of th e host images the proposed approach can easily handle gray-scale Images. As the result, stable reconstruction can be obtained even when the images are transformed, JPEG lossy compression or otherwise modified by low-pass filtering operations.

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Low-Power Sigma-Delta ADC for Sensor System (센서 시스템을 위한 저전력 시그마-델타 ADC)

  • Shin, Seung-Woo;Kwon, Ki-Baek;Park, Sang-Soon;Choi, Joogho
    • Journal of IKEEE
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    • v.26 no.2
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    • pp.299-305
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    • 2022
  • Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

Hardware Implementation of FPGA-based Real-Time Formatter for 3D Display (3D 디스플레이를 위한 FPGA-기반 실시간 포맷변환기의 하드웨어 구현)

  • Seo Young-Ho;Kim Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.5
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    • pp.1031-1038
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    • 2005
  • In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.

Semi-Fragile Image Watermarking for Authentication Using Wavelet Packet Transform Based on The Subband Energy (부대역 에너지 기반 웨이블릿 패킷 변환을 이용한 인증을 위한 세미 프레자일 영상 워터마킹)

  • Park, Sang-Ju;Kwon, Tae-Hyeon
    • The KIPS Transactions:PartB
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    • v.12B no.4 s.100
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    • pp.421-428
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    • 2005
  • A new method of Semi-fragile image watermarking which ensures the integrity of the contents of digital image is presented. Proposed watermarking scheme embeds watermark in the form of quantization noise on the wavelet transform coefficients in a specific mid frequency subbands selected from a wavelet packet decomposition based on energy distribution of wavelet transform coefficients. By controlling the strength of embedded watermark using HVS (Human Visual System) characteristic, it is imperceptible by a human viewer while robust against non-malicious attack such as compression for storage and/or transmission. When an attack is applied on the original image, it is highly probable that wavelet transform coefficients not only at the exact attack positions but also the neighboring ones are modified. Therefore, proposed authentication method utilizes whether both current coefficient and its neighbors are damaged. together. So it can efficiently detect and accurately localize attacks inflicted on the content of original image. Decision threshold for authentication can be user controlled for different application areas as needed.

Performance Analysis for Digital watermarking using Quad-Tree Algorithm based on Wavelet Packet (웨이블렛 패킷 기반 쿼드트리 알고리즘을 이용한 디지털 워터마킹의 성능 분석)

  • Chu, Hyung-Suk;Kim, Han-Kil;An, Chong-Koo
    • Journal of the Institute of Convergence Signal Processing
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    • v.11 no.4
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    • pp.310-319
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    • 2010
  • In this paper, digital watermarking method using wavelet transform and quad-tree algorithm is proposed. The proposed algorithm transforms the input image by DWT(Discrete Wavelet Transform) and AWPT(Adaptive Wavelet Packet Transform), inserts the watermark by quad-tree algorithm and the Cox's algorithm. The simulation for performance analysis of the proposed algorithm is implemented about the effect of embedding watermark in each subband coefficient (HH, LH, HL) of DWT, each DWT level, and each AWPT level. The simulation result by using DWT is compared with that using AWPT in the proposed algorithm. In addition, the effect of embedding watermark in the lowest frequency band (LL) is simulated. As a simulation result using DWT, the watermarking performance of simultaneously embedding in HH, LH, and HL band of DWT(6 level) is better than that of different cases. The result of AWPT(3 level) improves the correlation value compared to that of DWT(3 level). In addition, insertion the watermark to the LL band about 30~60% of all watermarks improves the correlation value while PSNR performance decreases 1~2dB.

Design of Digital Automatic Gain Controller for the IEEE 802-11a Physical Layer (고속 무선 LAN을 위한 디지털 자동 이득 제어기 설계)

  • 이봉근;이영호;강봉순
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2001.06a
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    • pp.101-104
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    • 2001
  • In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

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