• Journal of Korea Multimedia Society
• /
• v.11 no.9
• /
• pp.1258-1266
• /
• 2008

Most game players obtain more satisfactions by interacting with human players that have fluxed behavior patterns, than with NPC(Non-Player Character)s that have fixed behavior patterns. Since it is impossible that game players always interact with human players, adaptive NPCs that can variously behave are required. In this paper, we present a method to create adaptive NPCs using a dynamic FSM(Finite State Machine). This method configures a dynamic FSM by using behavior information at behavior database, and repeatedly updates the dynamic FSM so that the dynamic FSM's total efficiency approaches to a given target efficiency. NPC adapts to game players through this process. For an experiment, we have implemented a 2D game with this strategy, and experimented with various target efficiencies. We show that a dynamic FSM's total efficiency approaches to target efficiency by updating a dynamic FSM several times over. It means that the adaptive NPC to be generated, adapts to game players.

• Proceedings of the Korean Information Science Society Conference
• /
• 2004.04b
• /
• pp.550-552
• /
• 2004

가상공간에는 PC(Playerable Character), NPC(Non-Playerable Character)등의 동적 객체와 건물, 지형 등의 정적 객체들이 존재하게 된다. 동적 객체들의 경우, 현실감을 위해 인공지능이 자주 이용된다 현재까지 인공지능에 대한 연구는 유한상태기계(Finite State Machine. FSM). 학습 알고리즘, 유전자 알고리즘, 신경망 알고리즘 등을 중심으로 진행되어 왔다. 이중 유한상태기계는 비교적 알고리즘이 간단하고, 시스템의 부담이 적어 간단한 객체의 인공지능으로 가장 널리 사용되고 있다. 본 논문은 유찬상태기계를 확장하여 모드변경(Mode Change)과 그룹행동을 보여줄 수 있는 XML을 활용한 FSM 시스템을 제안한다. 여기서 모드변경이란 하나의 행동 패턴에서 다른 행동 패턴으로 변경하는 것을, 그룹행동은 여러 객체가 함께 행동하는 Flocking기법을 지칭한파. 이러한 XML을 활용한 FSM 시스템은 다양한 패턴의 정의는 물론, 객체의 상태 정의 및 수정, 확장이 용이하여, 다양한 응용 분야에서 활용될 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.8
• /
• pp.619-630
• /
• 2003

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

• Electronics and Telecommunications Trends
• /
• v.13 no.6 s.54
• /
• pp.94-107
• /
• 1998

연구 개발의 주된 내용은 SDL(Specification Description Language)을 위한 정형기법 지원도구 중 명세상에서 행위 부분에 대한 동적 특성을 검정하는 검정기 개발이다. 모델 검정기는 해당 프로토콜에 대해 생성된 중간 모델 I/O FSM(Input/Output Finite State Machine)에 Modal-calculus에 의해 검정대상인 deadlock, livelock, reachability 및 liveness에 대한 표현과 I/O FSM에 대해 해당 알고리즘 적용 및 분석 기능을 C++언어로 구현하였다. 또한 SDL Editer 기능과 관련된 도구들과 통합하여 사용자들이 쉽고 편하게 쓸 수 있도록 환경 및 통합 모듈을 구현한다.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2016.07a
• /
• pp.319-320
• /
• 2016

본 논문에서는 게임 개발에 있어서 빈번하게 적용되고 있는 식물 생태계와 이와 연동하는 동물 생태계를 자동화 하는 기법을 연구하고, 이를 실제로 구현하는 것을 목적으로 한다. 정해진 몇 가지 변수에 의해 자동 생성된 식물 생태계와 추가적인 FSM을 기반으로 생성되는 동물 생태계의 자동 생성 로직을 설계하고 이를 구현함으로써 기존의 게임 개발 과정에 효율성을 증대시키고, 최근 들어 터레인의 동적인 구성이나 유저와의 다양한 상호작용으로 인하여 빈번하게 요구되고 있는 자동화된 생태계 생성 기능을 구현하여 게임의 다양성이 기여하고자 한다. 본 논문에서 연구된 연구 결과는 추후에 일반적인 온라인 게임의 배경 자동 생성 시스템으로 확장되어 보다 다양한 적용이 가능할 것이다.

• Journal of KIISE:Information Networking
• /
• v.28 no.3
• /
• pp.355-368
• /
• 2001

Protocol conformance test is used to promote interoperability of protocol implementatons developed by venders. Non-interopcrability between protocol implementations may be caused by ambiguity and/or misintellJretation of the protocol specifications by vendors. Conventional method on protocol conformance test has been standardized by IS0;IEC JTCI with the purpose of whether a protocol implementation conforms to its specification. However, sometimes the conventional method gives wrong test results because the test is based on static test sequences. This problem is caused by the fact as some failed transitions of a protocol FSM included in test sequences have an effect on the test result of transitions to be tested. In this paper, a new approach called Dynamic Conformance Test Method (DCTM) is proposed to solve this problem. DCTM dynamically selects test sequence durng testing depending on an information showing an alternative path without failed tranistions. As a result, the fault coverage of the DCTM is better than that of the conventional test method. In order to demonstrate the fault coverage of DCTM compared to that of the conventional method. a testing tool is implemented and appied to the TCP protocol.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.2
• /
• pp.51-51
• /
• 2001

본 논문은 디지털 순서회로 설계시 상태할당 알고리즘 개발에 관한 연구로, 동적 소비전력을 감소시키기 위하여 상태변수의 변화를 최소로 하는 코드를 할당하여 상태코드가 변화하는 스위칭횟수를 줄이도록 하였다. 상태를 할당하는데는 Markov의 확률함수를 이용하여 hamming거리가 최소가 되도록 상태 천이도에서 각 상태를 연결하는 edge에 weight를 정의한 다음, 가중치를 이용하여 각 상태들간의 연결성을 고려하여 인접한 상태들간에는 가능한 적은 비트 천이를 가지도륵 모든 상태를 반복적으로 찾아 계산하였다. 비트 천이의 정도를 나타내기 위하여 cost 함수로 계산한 결과 순서회로의 종류에 따라 Lakshmikant의 알고리즘보다 최고 57.42%를 감소시킬 수 있었다.

• Journal of Internet Computing and Services
• /
• v.2 no.1
• /
• pp.1-11
• /
• 2001

Though it is proposed to use Petri net or dynamic FSM methods for the generation of test sequences on some specific protocols, those methods ere unavailable on the cases where the protocol allows faults processing or includes paths in looping which cause errors or endless looping by the explosion of states. The determination of test coverage on the protocol software that has been designed and implemented is difficult by the reason of development periods, technical solutions to support and also economical limitations. It is suggested to generate timely protocol software test sequences on the basis of regular expressions covering the functions of protocol. With this regular expression method, the 38 test sequences of Q.2971 protocol has been generated and also minimized the endless looping problem when dynamic test suites are used by simplifying the test path expressions that denotes loops, According to the works, the suggested method is confirmed as simple and easy compare to the other dynamic test sequence generation techniques. Moreover. the method to search an optional test path whether it Is included or not in the regular path expression is reviewed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.2
• /
• pp.137-144
• /
• 2001

In this paper, a state assignment algorithm was proposed to reduce power consumption in control-flow oriented finite state machines. The Markov chain model is used to reduce the switching activities, which closely relate with dynamic power dissipation in VLSI circuits. Based on the Markov probabilistic description model of finite state machines, the hamming distance between the codes of neighbor states was minimized. To express the switching activities, the cost function, which also accounts for the structure of a machine, is used. The proposed state assignment algorithm is tested with Logic Synthesis Benchmarks, and reduced the cost up to 57.42% compared to the Lakshmikant's algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.3
• /
• pp.48-54
• /
• 2000

This paper exploits the use of don't cares on software synthesis for embedded systems. Embedded systems have extremely tight real-time and code size constraints. We propose applying BDD minimization techniques in the presence of a don't care set to synthesize code for extended Finite State Machines from a BDD-based representation of the FSM transition function. The don't care set can be derived from local analysis as well as from external information. We show experimental results, discuss their implications, the interactions between BDD-based minimization and dynamic variable reordering, and propose directions for future research.