Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Reconfigurable SoC Design with Hierarchical FSM and Synchronous Dataflow Model

Hierarchical FSM과 Synchronous Dataflow Model을 이용한 재구성 가능한 SoC의 설계

  • 이성현 (서울대학교 전기컴퓨터공학부) ;
  • 유승주 (서울대학교 전기컴퓨터공학부) ;
  • 최기영 (서울대학교 전기컴퓨터공학부)
  • Published : 2003.08.01
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Abstract

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

본 논문은 최근에 많이 사용되는 정형 계산 모델 중 하나인 hierarchical FSM (HFSM)과 synchronous dataflow (SDF) 모델(줄여서 HFSM-SDF)을 이용한 재구성 가능한 SoC 설계에서 실시간 구성 스케줄링(configuration scheduling) 방법을 제시한다. HFSM-SDF 모델을 이용한 재구성 가능한 SoC 설계에서는 HFSM이 갖는 동적인 특성들(예를 들면, AND 관계에 의해 동시에 일어나는 state transition, HFSM이 갖는 복잡한 control flow, 그리고 그에 따른 SDF actor firing의 복잡한 스케줄등)로 인해 구성 스케줄링이 어려운 일이 된다. 그리고 이러한 동적인 특성들로 인해 정적인 구성 스케줄링 방법을 이용해서는 구성에 의한 지연(configuration latency)을 적절히 감추는 것이 어렵다. 본 논문에서는, 이 문제를 해결하기 위해, 실시간에 정확한 구성 순서를 찾은 후, 이를 이용한 동적인 구성 스케줄링 방법을 제안한다. 우선, 실시간에 필요한 구성 순서를 찾기 위해서는, HFSM-SDF 모델이 갖는 특징, 즉, SDF actor들의 실행 순서(firing schedule)는 최상위 FSM state transition 직전에 알 수 있다는 점을 이용할 수 있다. 이렇게 최상위 FSM의 매 transition마다 SDF actor들의 구성 순서를 찾아, ready configuration queue(ready CQ)에 저장한 후에, 전체 시스템의 state transition을 수행하며, 이 과정에서 FPGA에 (기존에 FPGA를 점유하고 있던 SDF actor의 종료 등으로 인해) 공간이 남으면, 실시간 구성스케줄러는 ready CQ를 살펴보고, 필요한 구성을 다운로드한다. 본 논문에서 제시한 실시간 구성 방법을 MPEG4의 natural video decoder와 IS95의 modem 예제에 적용해 본 결과, 수행 시간이 최대 21.8%까지 향상되었으며 메모리 사용의 부담은 무시할 수 있을 정도였다.

Keywords

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