• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.4
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• pp.721-725
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• 2007

A fiber optic based weight sensor has fabricated using a fiber Bragg grating with a weight sensitive. The sensing concept exploits the inherent characteristics of the FBG and is based on the strain effect induced in the fiber Bragg grating through. A direct indication of the weight level is given by the shift of the Bragg wavelength caused by the expansion of the sensing material. A FBG behaves like a spectral filter which has inherent characteristics that render it very sensitive to strain and temperature. The sensing principle is also based on the strain effect induced in the FBG through the caused by the weight. The experimental setup used for the initial investigation to characterize the mass response of the sensor. The transmitted signal from the sensor was monitored using an optical spectrum analyzer with a resolution bandwidth of 0.4nm. In this paper, we presented the spectral characterization and shaping of FBG by scanning a mass element that affects a small grating fraction at a time, without permanent effects on the optical fiber when the various wavelength and strain is removed. That is, destruction when the optical fiber for weight is physically damaged.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Journal of the Korean Society of Hazard Mitigation
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• v.11 no.1
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• pp.23-27
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• 2011

Due to the rapid development of construction technology with effective land utilization in this nation, many tunnels were and are being built across the country. However, the smoke and the heat generated from tunnel fire are the most important critical factors which may results in both massive personal injury and property damage, especially, due to the closed surrounding of the tunnel. Considering this particular nature of the tunnels, this study aims to install a fire detection system using an optic fiber cable to measure the temperature changes, compare, and analyze the resulted values with the times of temperature changes of the sensor by performing fire simulations under the same condition as a real fire test. From the results, it has been found that the temperature sensor detects a fire occurrence and generates an alarm within one minute after ignition for both a real fire test and a fire simulation alike, and also that the characteristics of temperature changes of the sensor has close relations with the speeds of the currents inside the tunnel. In addition, considering the tunnel fires can affect the evacuation efficiency and the fire extinguishing activities of the fire brigade inside the tunnel, the temperature sensor must be able to search and find the locations and directions of the fires correctly.

• Journal of IKEEE
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• v.25 no.3
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• pp.467-472
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• 2021

Stable operation of semiconductor devices is needed even at high temperatures. Among the structures of semiconductor devices, the area that can cause unstable electrical responses at high temperatures is the contact layer between the metal and the semiconductor. In this study, the effect of annealing conditions included in the process of forming a contact layer of nickel silicide(NiSix) on a p-type SiC layer on the specific contact resistance of the contact layer and the total resistance between the metal and the semiconductor was investigated. To this end, a series of electrodes for TLM (transfer length method) measurements were patterned on the 4 inch p-type SiC layer under conditions of changing annealing temperature of 1700 and 1800 ℃ and annealing time of 30 and 60 minutes. As a result, it was confirmed that the annealing conditions affect the resistance of the contact layer and the electrical stability of the device.

• Journal of Digital Convergence
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• v.16 no.12
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• pp.647-654
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• 2018

This study was designed to compare the effects of individual sensory integration treatments on the improvement of motor skills and group psychomotorik activities that produce a wide range of interactions with peers. The research targets two 4-year-old children, who are currently in the main building, and 40 minutes of psychomotorik and sensory integration treatment were applied to them twice a week from April 2017 to January 2018. The study method used assessment tools such as B-O test, DeGangi-Berk Test of Sensory Integration (TSI), and MOT4-6 respectively. The results of the study showed that programs in both areas had positive effects on motor skills, with significantly improved performance in balance and postural control, in particular.

• The Journal of Korean Institute of Information Technology
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• v.17 no.7
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• pp.31-45
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• 2019

The core technologies for intelligent services today are deep learning, that is neural networks, and parallel and distributed processing technologies such as GPU parallel computing and big data. However, for intelligent services and knowledge sharing services through globally shared ontologies in the future, there is a technology that is better than the neural networks for representing and reasoning knowledge. It is a knowledge representation of IF-THEN in RIF or SWRL, which is the standard rule language of the Semantic Web, and can be inferred efficiently using the rete algorithm. However, when the number of rules processed by the rete algorithm running on a single computer is 100,000, its performance becomes very poor with several tens of minutes, and there is an obvious limitation. Therefore, in this paper, we analyze the past and current studies on parallel and distributed processing of rete algorithm, and examine what aspects should be considered to implement an efficient rete algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.49-56
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• 2004

The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

• Science of Emotion and Sensibility
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• v.14 no.4
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• pp.571-580
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• 2011

The purpose of this study was to evaluate the effects of secondary task such as sending text message (STM) and searching navigation (SN) using the variable indicating control of vehicle ((Medial-Lateral Coefficient of Variation, MLCV), (Anterior-Posterior Coefficient of Variation, APCV)) and motion signal (Jerk-Cost function, JC). Participants included 50s taxi drivers; 14 males and 14 females. Participants were instructed to keep a certain distance (30m) from the car ahead with constant speed (80km/hr or 100km/hr). Experiement consisted of driving alone for 1minute and driving with secondary task for 1minute. Both MLCV and APCV were significantly increased during Driving + Sending Text Message(STM) and Driving + Searching Navigation(SN) than Driving only. Also, JC was increased during Driving + STM and Driving + SN than Driving only. In this study, we found that even in the experts group who are taxi driver and have 25 years driving experience, the smoothness of motion is decreased and the control of vehicle is disturbed when they were performing secondary tasks like sending text message or searching navigation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.