• Journal of the Korean Vacuum Society
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• v.14 no.4
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• pp.207-214
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• 2005

This paper presents a channel structure for promising high performance pseudomorphic high electron mobility transistor(pHEMT) switching device for design and fabricating of microwave control circuits, such as switches, phase shifters, attenuators, limiters, for application in personal mobile communication systems. Using the designed epitaxial channel layer structure and ETRI's $0.5\mu$m pHEMT switch process, single pole double throw (SPDT) Tx/Rx monolithic microwave integrated circuit (MMIC) switch was fabricated for 2.4 GHz and 5 GHz band wireless local area network (WLAN) systems. The SPDT switch exhibits a low insertion loss of 0.849 dB, high isolation of 32.638 dB, return loss of 11.006 dB, power transfer capability of 25dBm, and 3rd order intercept point of 42dBm at frequency of 5.8GHz and control voltage of 0/-3V These performances are enough for an application to 5 GHz band WLAN systems.

• Journal of KIISE:Information Networking
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• v.33 no.6
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• pp.407-419
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• 2006

As substituting IPv6 network for all IPv4 network in a short time seems unattainable due to high cost and technical limitation, IPv4 and IPv6 are expected to coexist for a certain period of time. Under the co]existing environment of IPv4 and IPv6, interworking brings a number of extra security considerations even if it may have no security problem for each protocol respectively. Thus, the analysis and solutions for those various attacks toward IPv4/IPv6 interworking-related security are inevitably required for the sake of effective transition and settlement to IPv6. In this paper we carried out a proper rule of packet filtering for IPv6-in-IPv4 tunneling interworking environment to protect the IPv4/IPv6 interworking-related security attacks. Design and implementation of the packet filtering system suitable for IPv4/IPv6 tunneling environment in the form of Linux netfilter and ip6tables are also shown. Thru this study, the packet filtering system was found operating correctly ill the tunneling mechanism.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.600-608
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• 2016

This paper proposes a new high-efficient interleaved phase-shift full-bridge (PSFB) converter for low-voltage and high-current power systems. The proposed converter is composed of three switch-bridges and two transformers in the primary side and two rectifiers in the secondary side. Each transformer handles half of the total power with an interleaved operation, so that the proposed converter has high system reliability, as much as the conventional interleaved PSFB converter. The soft-switching characteristics of the proposed converter are better than those of the conventional converter due to the modulated primary side configuration. The proposed converter represents a single lagging-leg bridge, which has a poor soft switching condition in its operation, while the conventional converter has two lagging-leg bridges in its operation. Therefore, the number of switches having hard-switching conditions is reduced by half in the proposed converter. In addition, the reduced switch counts in the primary side of the proposed converter helps decrease the complexity of the proposed converter compared to that of the conventional converter. The operational principle and analysis are presented in this paper and the characteristics are verified using a PSIM simulation with 3kW server power specification.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.504-510
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• 2017

This paper presents an AC-DC power module design and evaluates its efficiency and reliability when used for electronics appliances. This power module consists of a PWM control IC, power MOSFETs, a transformer and several passive devices. The module was tested at an input voltage of 220V (RMS) (frequency 60 Hz). A test was conducted in order to evaluate the operation and power efficiency of the module, as well as the reliability of its protection functions, such as its over-current protection (OVP), overvoltage protection (OVP) and electromagnetic interference (EMI) properties. Especially, we evaluated the thermal shut-down protection (TSP) function in order to assure the operation of the module under high temperature conditions. The efficiency and reliability measurement results showed that at an output voltage of 5 V, the module had a ripple voltage of 200 mV, power efficiency of 73 % and maximum temperature of $80^{\circ}C$ and it had the ability to withstand a stimulus of high input voltage of 4.2 kV during 60 seconds.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1899-1909
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• 2007

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Korean Journal of Optics and Photonics
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• v.29 no.6
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• pp.275-284
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• 2018

In this study we propose a hybrid color-filter design method in which a nanohole array and a nanodisk array are separated by nanopillars of the material AZ 1500. We propose a design method for an RGB color filter, using the tendency of transmitted light according to each design variable. Especially we analyzed the intensity distribution of the electric field in the cross section, and set the height of the nanopillars so that the local surface-plasmon resonances generated in the two different arrays do not affect each other. The optical characteristics of the optimized color filter are as follows: In the case of the red filter, the ratio of the wavelength band expressing red in the visible broadband is 55.01%, and the maximum transmittance is 41.53%. In the case of the green filter, the ratio of the wavelength band expressing green is 40.20%, and the maximum transmittance is 42.41%. In the case of the blue filter, the ratio of the wavelength band expressing blue is 32.78%, and the maximum transmittance is 30.27%. We expect to improve the characteristics of color filters integrated in industrial devices by this study.

• Journal of Navigation and Port Research
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• v.42 no.6
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• pp.421-426
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• 2018

With regard to LED lighting devices which have currently been commercialized, LED operating sequences are being sold in a fixed state. In such a state, the external environmental factors are not taken into consideration as only the illumination environment application is considered. Currently, it is difficult to create an optimal lighting environment which can adapt to changes in external environmental factors in the ship. Therefore, it was concluded that there is a need to input the external environment value so that the optimal illumination value can be reflected in real time in order to adapt more organically and actively to the change of external environmental factors. In this paper, we used a microprocessor as an integrated management system for environmental data that changes in real time according to existing external environmental factors. In addition, a controller capable of lighting control of RGB LED module by combining fuzzy inference system. For this, a fuzzy control algorithm is designed and a fuzzy control system is constructed. The distance and the illuminance value from the external environment element are input to the sensor, and these values are converted to the optimum illumination value through the fuzzy control algorithm, and are expressed through the dimming control of the RGB LED module and the practical effectiveness of the fuzzy control system is confirmed.