• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.3
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• pp.6-11
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• 2006

This paper describes the novel control techniques design of VSC(Voltage Sag Corrector) for the purpose of power line quality enhancement. A fast detecting technique of voltage sag is implemented through the detection of instantaneous value on synchronous rotating dq-reference frame. The first order digital filter is added in the detection algorithm to protect the insensitive characteristics against the noise. The relationship between the total detection time and cut-off frequency of the filter is described. The size of the capacitor bank used as the energy storage element is designed from the point of view of input/output energy with circuit analysis. Finally, the validity of the proposed scheme is proven through the simulated results.

• Journal of Radiation Protection and Research
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• v.38 no.3
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• pp.132-137
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• 2013

Cryogenic particle detectors have recently been adopted in radiation detection and measurement because of their high energy resolution. Many of these detectors have demonstrated energy resolutions better than the theoretical limit of semiconductor detectors. We report the development of alpha spectrometer using a micro-fabricated magnetic calorimeter coupled to a large-area particle absorber. A piece of gold foil of $2{\times}2{\times}0.05mm^3$ was glued to the paramagnetic temperature sensor made of sputtered Au:Er film to serve as an absorber for incident alpha particles. We performed experiments with 241Am source at cryogen free adiabatic demagnetization refrigerator (CF-ADR). A high energy resolution of 6.8 keV in FWHM was obtained for 5.5 MeV alpha particles.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.24-30
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• 2007

In this paper, an energy detection-based low power, low complexity IR-UWB receiver in multipath impulse radio channel is presented. The proposed receiver has a simple 1-bit sampler for energy detection. Also, multipath signal received from multipath impulse radio channel is amplified and envelope of the signal is detected. Then, energy detection technique using integrator by summing multipath signals in certain period is adopted to minimize the BER loss by simple energy detection. In particular, in acquisition of a sample signal, SNR is additionally improved using a digital sampler. Symbol decision using several sampled signals is performed and thus the process of symbol synchronization is significantly simplified. Also, it is effectively designed to be compatible with influences of multipath and timing error. In addition, the proposed receiver complexity is reduced using pulse decision window. The performance of the proposed receiver is simulated based on IEEE 802.15.4a channel model and the algorithms are implemented on FPGA.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.81-90
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• 2002

This paper presents an Implementation of digital high-performance position sensorless control system of Reluctance Synchronous Motor(RSM) drives with Direct Torque Control(DTC). The system consists of stator flux observer, speed and torque estimator, two digital hysteresis controllers, an optimal switching look-up table, Insulated Gate Bipolar Transistor(IGBT) voltage source inverter, and TMS320C31 DSP board. The stator flux observer Is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current and voltage sensed on motor terminal for wide speed range. In order to prove the suggested sensorless control algorithm for industrial field application, we have some simulation and actual experiment at low and high speed range. The developed high-performance speed control by fully digital system are shown a good response characteristic of control results and high performance features using 1.0[kW] RSM having 2.57 reluctance ratio of $L_d/L_q$.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.4
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• pp.309-316
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• 2011

A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.7
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• pp.545-551
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• 2013

Timing recovery loop composed of the Timing Error Detector(TED), loop filter and resampler is widely used for the timing synchronization in MQASK receivers. Since TED is sensitive to the delay between the symbol period of the signal and sampling period, the output is averaged out when the symbol rate and sampling rate are quite different the recovery loop cannot work at all. This paper presents a sampling frequency discriminator (SRD), which detects the frequency offset of the sampling clock to the symbol clock of the MQASK data transmitted. Employing the SRD, the closed loop timing recovery scheme performs the frequency-aided timing acquisition and achieve the synchronization at extremely high sampling frequency offset, which can be used in variable symbol rate MQASK receivers.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.271-272
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• 2011

본 논문은 SOGI를 이용한 정상분 전압 검출을 기반으로 하는 SRF(synchronous reference frame)-PLL(phase locked loop) 시스템을 제안한다. 일반화된 2차 적분기의 이중으로 사용하여 QSG(Quadrature-signals generator)의 성능을 개선하여 전압 불평형, 고조파 왜곡 등으로 인한 오차 발생 시에도 빠르고 정확한 위상 검출이 가능하도록 하였으며 본 논문에서 제시한 알고리즘은 PSIM 프로그램 결과를 통하여 타당성을 입증한다.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.3
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• pp.65-70
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• 2008

Capacitive position sensing with modulation technique is widely used in electrostatic actuator applications. To maximize the electrostatic force and the position-sensing gain, capacitors for driving and capacitors for sensing are shared, i.e, after applying the driving voltage with high-frequency modulating signals using op amps, the position is demodulated from the modulated signal. In high-voltage applications, however, low bandwidth of a high-voltage op amp hinders adding the high-frequency modulating signal to the driving voltage. In this paper, new and very simple driving and sensing method is proposed, in which the pulse-width modulated driving voltage eliminates the need of the high-frequency modulating signal for position sensing. This new algorithm is proved by the simulation results using Matlab/SIMULINK.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.222-226
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• 2001

본 논문에서는 단상 H-bridge 구조의 VSC (Voltage Source Converter)를 이용하여 계통전원을 사용하는 부하의 고조파 전류 보상기능과 전원 Back-up 기능을 갖는 부하전력보상기를 보여준다. 이 두 제어 기능은 전원전압의 유무에 따라 APF의 컨버터 동작과 UPS의 인버터로 동작하게 함으로써 기존 UPS에 부하 전류의 고조파 보상이라는 부가적인 이득을 갖는 이중전력보상기(Dual Function Power Compensator)라 할 수 있다. 컨버터 제어는 Battery 충전 동작과 APF 동작을 동시에 수행하며, 인버터 제어는 정전시 부하에 전원을 공급하는 UPS로서의 동작을 수행하게 된다. 두가지 동작이 성공적으로 수행되기 위해서는 1. 전원전압의 신속한 검출과 판단, 2. 컨버터의 Battery 충전, 3. APF동작을 위한 부하전류의 고조파 전류계산, 4. 전원전압의 동기추종 등이 각각의 동작모드별로 순조롭게 연계동작 되어 야 한다. 본 논문에서는 DFPC의 발생배경과 제안된 DFPC 제어모드의 구분을 결정하는 전원전압의 검출방법에 대하여 소개한다. 그리고 제안된 DFPC의 실제 시스템을 제작하여 각각의 동작상황과 성능을 시험하여 그 결과를 보여준다.