• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.756-763
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• 2005

본 논문에서는 KOSPI200 지수선물의 분 단위 가격 데이터를 이용하여 거래비용을 고려한 옵션 복제 전략들의 성과를 비교하였다. 비교를 위해 사용한 옵션 복제 전략들은 (1)Black-Scholes 델타(delta) 전략, (2)Black-Scholes 델타 한도 전략, (3)Leland 전략, (4)Whalley-Wilmott 전략이다. 각 전략들은 옵션 복제를 위한 기초자산 거래와 관련된 두 가지 질문에 대한 답을 준다. 첫 번째 질문은 거래 시점에 관한 것으로, '언제 거래할 것인가'이고, 두 번째 질문은 거래량에 관한 것으로, '얼마만큼 거래할 것인가'이다. 본 논문에서는 현실적인 KOSPI200 지수선물 거래수수료(거래금액 대비 0.01%) 환경에서 잔존만기 1년인 유럽형 등가격 콜 옵션을 복제하는 경우를 실험하였다. 실험 결과 Leland 전략을 제외한 나머지 세 전략들의 복제 성과가 상대적으로 뛰어난 것으로 나타났다. 그러나 이들 세 전략들 간에는 복제 성과에 대해 뚜렷한 차이를 발견하기 어려웠다. 한편, 복제 종료 시점에서의 복제 손익에 큰 영향을 미치는 요인은 복제 오차(복제 포트폴리오의 만기 가치와 복제 대상 옵션의 만기 현금흐름의 차이)인 것으로 나타난 반면, 복제를 위한 기초자산 거래비용이 복제 종료 시점에서의 복제 손익에 미치는 영향은 적은 것으로 나타났다.

• 한국전산유체공학회:학술대회논문집
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• 2006.10a
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• pp.31-35
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• 2006

The delta-formulation of the Navier-Stokes equations has been popularly used in the aerodynamics area. Implicit algorithm can be easily implemented in that by using Taylor series expansion. This formulation is extended for an unsteady analysis by using a dual-time integration. In the meanwhile, the incompressible flows with heat transfers which occur in the area of thermo-hydraulics have been solved by a segregated algorithm such as the SIMPLE method, where each equation is discretised by using an under-relaxed deferred correction method and solved sequentially. In this study, the dual-time delta formulation is implemented in the segregated Navier-Stokes solver which is based on the collocated cell-centerd scheme with un unstructured mesh FVM. The pressure correction equation is derived by the SIMPLE method. From this study, it was found that the Euler dual-time method in the delta formulation can be combined with the SIMPLE method.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.912-916
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• 1992

In this paper we investigate the connection between the continuous-time FIR(finite impulse response) filter and the corresponding discrtet-time FIR filter with fast sampling. The interconnection is established by formulating the discrete-time case using delta operators which has superior numerical properties in discretizing prcedure. The aim of this paper is to present a unified FIR filter using the .delta.-operator and to show that, as sampling interval .DELYA. aperator to zero, the results of this filter converge to the corresponding continuous-time reuslts, which implies that the unified FIR filter unifies continous-time FIR filter and discrtet-time FIR filter.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• Journal of Gastric Cancer
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• v.5 no.1
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• pp.16-22
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• 2005

Purpose: In Korea, the number of laparoscopy-assisted distal gastrectomies for early gastric cancer patients has been increasing lately. Although minimally invasive surgery is more beneficial, no reported case of a totally laparoscopic distal gastrectomy has been reported because of difficulty with intracorporeal anastomosis. This study attempts, through our experiences, to determine the feasibility of a totally laparoscopic distal gastrectomy using an intracorporeal gastroduodenostomy in treating early gastric carcinoma. Materials and Methods: We investigated surgical results and clinicopatholgic characteristics of eight(8) patients with an early gastric carcinoma who underwent a totally laparoscopic distal gastrectomy at the Department of Surgery, Our Lady of Mercy Hospital, The Catholic University of Korea, between June 2004 and September 2004. The intracorporeal gastroduodenostomy was performed with a delta-shaped ananstomosis by using only laparoscopic linear staplers (Endocutter 45mm; Ethicon Endosurgery, OH, USA). Results: The operative time was $369.4\pm62.5$ minutes (range $275\∼465$ minutes), and the anastomotic time was 45.1\pm14.4$ minutes (range $32\∼70$ minutes). The anastomotic time was shortened as surgical experience was gained. The number of laparoscopic linear staplers for an operation was $7.1\pm0.6$. The number of lymph nodes harvested was $31.9\pm13.1$. There was 1 case of transfusion and no case of conversion to an open procedure. The time to the first flatus was 2.8$\pm$0.5 days, and the time to the first food intake was $4.1\pm0.8$ days. There were no early postoperative complications, and the postoperative hospital stay was $10.0\pm3.9$ days. Conclusion: A totally laparoscopic distal gastrectomy using an intracorporeal gastroduodenostomy with a delta-shaped anastomosis is technically feasible and can maximize the benefit of laparoscopic surgery for early gastric cancer.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.177-179
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• 2019

본 논문은 리튬폴리머 배터리를 기반으로 한 40 kV 펄스전원장치의 설계를 다룬다. 기존에 설계된 펄스전원장치는 삼상 380 V AC 입력 전원을 통해 구동되었으나, 이를 배터리 기반 2 kW 용량의 고전압 충전기를 통해 구동하도록 설계한다. 이 고전압 충전기는 44 V 리튬 폴리머 배터리를 기반으로 2 kW의 출력 용량을 갖도록 삼상 델타-와이 변압기 구조의 LCC 공진형 컨버터로 제작된다. 이를 통해 설계된 펄스전원장치는 최대 전압 40 kV, 펄스 폭 1.5 us - 5 us, 최대 펄스 반복율 3 kHz의 사양을 갖는다. 본 논문을 통해 2 kW급 고전압 충전기의 설계 및 분석을 하고 시뮬레이션 결과, 실험 결과를 분석한다. 또한 배터리 기반 40 kV 펄스 전원 장치의 시스템을 설명하며, 저항부하 실험을 통해 안정적인 동작과 성능을 검증한다.

• Education of Primary School Mathematics
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• v.11 no.1
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• pp.1-19
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• 2008

This study analyzed the repeated error patterns in division of fraction by elementary students through observation of their test papers. The questions for this study were following. First, what is the most changable thing among the repeated error patterns appeared in division of fraction by elementary students? Second, what is the most frequent error patterns in division of fraction by elementary students? First of all, the ratios of incorrect answers in division of fraction by general students were researched. This research was the only one time. The purpose was to know what kind of compositions in the problems were appeared more errors. Total 554 6th grade students(300 boys and 254 girls) from 6 elementary schools in Seoul are participated in this research. On the basis of this, the study for analysis began in earnest. 5 tests made progress for about 4 months. Total 181 6th grade students(92 boys and 89 girls) from S elementary school in Seoul were participated in this. After each test, to confirm the errors and to classify them were done. Then the repeated error patterns were arranged into 4 types: alpha, beta, gamma and delta type. Consequently, conclusions can be derived as follows. First, most students modify their errors as time goes by even though they make errors about already learned contents. Second, most students who appeared errors make them continually caused a reciprocal of natural number in the divisor when they calculate computations about '(fraction) $\div$ (natural number)'. Third, most students recognize that the divisor have to change the reciprocal when they calculate division of fraction through they modify their errors repeatedly.

• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.18-20
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• 2007

3상 계통 연계 형 인버터 시스템은 낮은 THD를 가지는 계통 전류를 공급해주기 위해 LCL 필터를 사용한다. LCL 필터를 사용하는 가장 큰 장점은 낮은 스위칭 주파수에서도 만족할 만한 수준의 THD를 가지는 계통 전류를 생성시킬 수 있다는 점이다. 반면에, 단점은 LCL필터를 포함하는 계통 연계 형 인버터 시스템의 전달함수에 하나의 공진 극점이 존재한다는 점이다. 이것은 계통 전류 제어 loop에서, 안정성 문제에 영향을 미친다. 정확한 제어를 위해서 시스템의 전달함수는 필수적이다. 여기서 중요한 점은 많은 저자들이 시뮬레이션과 실험을 할 때, 중성점이 없는 회로에서 행하지만 회로 해석을 할 때에는 중성점이 있는 회로에서 해석을 한다는 점이다. 그래서 우리는 등가 델타회로에서 LCL 필터를 포함한 전체 시스템의 수학적인 모델을 제안한다. 이 모델은 모든 인덕터와 커패시터의 기생 저항을 고려한다. 또한 이 논문은 계통 전류를 제어하기 위한 제어기의 해석적인 설계 절차를 포함한다. 제안한 수학적인 모델을 입증하기 위해, PSIM을 통한 시뮬레이션과 Simulink를 통한 시뮬레이션 결과를 비교하였다.