• Journal of The Korean Association of Information Education
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• v.22 no.1
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• pp.169-176
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• 2018

CS Unplugged education at the base of computer science is emphasized as an instrument for teaching the basic principles of elementary SW education, but these materials for elementary education are very lacking. So We'll present the data error detection and correction materials for elementary school classes. Based on previous studies related to this topic, we developed learning materials for elementary higher grade students using Hamming code. We introduces the card magic in the introduction part. 'error detection and correction' learning materials based on the principle of Hamming code, were composed as activity-based education. The results of the questionnaire survey showed that it had a positive effect on improving learners' understanding of computer science.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.419-422
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• 2016

소프트웨어 품질 향상을 위해 결함을 조기에 발견/수정하는 것은 중요하며, 대부분의 소프트웨어 기업과 관련 커뮤니티는 이를 위해 테스트 단계에 노력을 집중하고있다. 하지만 테스트 단계에서 결함을 검출하는 것은 시기적으로 늦은 편에 속한다. 소프트웨어 결함 수정 비용은 결함의 발견 시기가 늦어질수록 급격하게 증가하기 때문에 테스트 단계에서의 소프트웨어 품질 향상 활동은 비효율적이다. 본 논문에서는 테스트 이전의 단계에서 조기에 결함을 발견/수정할 수 있는 코드 검토 방법을 더 효율적으로 활용 할 수 있는 방법을 제시한다. 제안하는 방법은 컴파일 에러 데이터를 저장하고 이를 통계적으로 분석한 데이터를 활용해 코드 검토를 수행하는 것이다. 이 방법을 적용하면 더 효율적으로 소프트웨어 품질 향상을 이끌어낼 수 있을 것으로 기대된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2634-2636
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• 2004

다목적실용위성2호의 위성 본체시스템에는 지상과 연락을 담당하는 주 컴퓨터인 OBC, 위성의 자세를 제어를 위한 원격구동장치인 RDU 그리고 위성의 전원분배를 제어장치인 ECU인 3개의 동일 프로세서(386)가 탑재되어 각 담당 임무를 수행하는 분산형 구조를 갖고 있다. 각 프로세서는 EEPROM과 SRAM 데이터 메모리를 갖고 있는데 전원 리셋이 일어나면 모든 프로그램은 EEPROM에서 SRAM으로 복사되어 운영 프로그램이 실행하도록 되어 있다. 그러나 SRAM은 우주환경에서 위성체는 방사선에 노출되어 손상을 입을 때 SEU이 발생되어 정보가 왜곡되거나 상실되는 문제를 갖고 있다. 그러므로 본 논문에서는 변형된 해밍코드 기법을 이용하여 데이터를 수신하는 곳에서 에러를 검출 및 수정하는 디지털 회로 설계방법을 기술하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.936-944
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• 2003

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %, maximum combinational path delay is reduced by 56.7 %, and maximum net delay is reduced by 80.5 % compared to conventional methods.