• Title/Summary/Keyword: 대기전력차단

Search Result 53, Processing Time 0.031 seconds

MTCMOS ASIC Design Methodology for High Performance Low Power Mobile Computing Applications (고성능 저전력 모바일 컴퓨팅 제품을 위한 MTCMOS ASIC 설계 방식)

  • Kim Kyosun;Won Hyo-Sig
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.42 no.2 s.332
    • /
    • pp.31-40
    • /
    • 2005
  • The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

A Low Leakage SRAM Using Power-Gating and Voltage-Level Control (파워게이팅과 전압레벨조절을 이용하여 누설전류를 줄인 SRAM)

  • Yang, Byung-Do;Cheon, You-So
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.49 no.8
    • /
    • pp.10-15
    • /
    • 2012
  • This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

Implementation of Smart Multi-tap System based on Zigbee Communication (Zigbee 통신 기반 스마트 멀티탭 시스템 구현)

  • Lee, Jung-Hyuck;Kim, Sang-Hyun;Oh, Chang-Se;Seo, Min-Seok;Kim, Young-Don;Park, Hyun-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.39C no.10
    • /
    • pp.930-936
    • /
    • 2014
  • Smart Multiple-Tap to be introduced in this paper, is an electronic device that controls the Multibple-Tap through the Smartphone. It runs on network and has an inbuilt Zigbee communication module. Thus, users can control home devices from remote through home server. Mentioned home server is operated as a gateway and is connected with smart devices on the Internet. To sum up, Users using this Smart Multiple-Tap can check the state information of the multi-tap ON/OFF and can control immediately by smartphone. also, Smart Multiple-Tap perfectly shut down the standby power. when users turn off each of the Smart Multiple-Tap's circle, It drives automatically lowest electricity-consuming mode and shut down the standby power by its own built-in SSR module. therefore, it will bring the energy saving effect on environment using Smart Multiple-Tap.