• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.33-34
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• 2013

본 논문은 양방향으로 동작하는 직렬 공진형 DC-DC 컨버터의 디지털 제어기 해석 및 설계에 대해 기술한다. LLC 양방향 공진형 컨버터 전력 변환단 동특성을 기반으로 소신호 해석을 이용한 디지털 제어기를 설계하고, DSP를 이용하여 디지털 제어기를 구현한다. 디지털 제어기는 Emulation 방식을 이용하여 설계한다. 개발된 디지털 제어기를 300W급 공진형 컨버터 실험보드에 적용하여 디지털 제어방식의 전원단의 동특성 및 폐루프 성능을 검증한다. 제어기 설계의 이론 검증 및 분석은 PSIM Simulation과 실험 측정으로 비교 검증한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.343-345
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• 2013

This paper describes a phase-locked loop (PLL) that generates a 51-phase clock with the operating frequency of 125MHz. To generate 51-phase clock with a frequency of 125 MHz, the proposed PLL uses three voltage controlled oscillators (VCOs) which are connected by resistors. Each VCO consists of 17 delay-cells. An resistor averaging scheme, which makes three VCOs to connect with each other, makes it possible to generates 51-phase clock of the same phase difference. The proposed PLL is designed by using 65 nm CMOS process with a 1.0 V supply. At the operating frequency of 125 MHz, the simulated DNL and peak-to-peak jitter are +0.0016/-0.0020 LSB and 1.07 ps, respectively. The area and power consumption of the implemented PLL are $290{\times}260{\mu}m^2$ and 2.5 mW, respectively.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.227-228
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• 2007

디지털기술의 발전으로 원자력발전소의 기기제어시스템은 Single-loop Control과 하드와이어드된 배선을 이용한 제어방식에서 Multi-loop Control과 통신망을 이용한 제어방식으로 변화되고 있다. 이에 따라 기기제어시스템의 단일고장발생시 플랜트 위험도가 증가하게 됨으로 플랜트 위험도 감소를 위한 연구가 필요하다. 위험도 감소를 위한 방안에는 기기제어시스템을 구성하는 기기의 신뢰도를 향상시키는 방법과 제어루프에 작동기기를 적절하게 배치하여 단일고장발생시 플랜트 위험도를 감소시키는 방법이 있다. 본 논문에서는 플랜트 위험도 감소 방안 중 작동기기 할당 방안에 대해 기술하였다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.357-358
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• 2014

본 논문에서는 태양광 모듈의 최대 전력점을 추종하기 위한 제어 기법으로 부스트 컨버터(boost converter)의 불연속 전류모드(Discontinuous Current Mode)에서 주파수를 제어하는 기법을 구현 하였다. 태양광 모듈에 연결된 부스트 컨버터는 전압루프를 통하여 Perturb and Observation(P&O)기법을 사용하여 최대 전력점을 추종하였다. 부스트 컨버터의 인덕터에 흐르는 전류는 불연속 전류모드로 제어 된다. 불연속 전류모드에서의 제어기 설계는 MATLAB과 PSIM의 전달함수특성을 수학적 모델링을 통하여 비교 검증 하였으며, 모든제어는 MCU(TEXAS INSTRUMENTS사의 DSPF28335)를 통해 디지털로 제어 하였다. 제안된 기법은 단일 PV모듈이 연결된 불연속전류모드 부스트 컨버터를 통해 동작특성을 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.380-381
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• 2011

본 논문에서는 PFC 부스트 컨버터의 역률 및 고조파 왜율 개선을 위한 전류 제어기 이득 조정 기법을 제안한다. PFC단은 입력 전압의 변화에 따라 인덕터 전류의 크기가 달라져 부스트 인덕터의 인덕턴스가 변화하게 되어 전류 루프의 주파수 특성이 변화하게 된다. 이러한 현상으로 인한 전류 루프의 이득 변화를 분석하였다. 이를 기반으로 입력 전압에 따라 전류 제어기의 이득을 조정해 줌으로써, 충분한 위상마진을 확보함과 동시에 PF와 THD 성능을 개선한다. TI사의 TMS320F28027 MCU를 이용한 실험을 통해 제안된 기법의 유용성을 검증한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.9
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• pp.711-723
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• 2017

This paper proposes a flight control system for an organic flight array(OFA) which has a new configuration to consist of multi modularized ducted-fan unmanned aerial vehicles (UAVs). The OFA is able to apply to various missions such as indoor reconnaissance, communication relay, and radar jamming by using capability of hover flight. The OFA has a distinguished advantage due to reconfigurable structure to assemble or separate with respect to its missions or operational conditions. A dynamic modelling of the OFA is derived based on equations of motion of the single ducted-fan modules. In order to apply nonlinear control method, an affine system of attitude dynamics is derived. Moreover, the control system is composed of a back-stepping controller for attitude control and a PID controller for position control. Then the performance of the proposed controller is verified via a numerical simulation under wind disturbance.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.72-78
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• 2005

This paper describes the design of a robust output-feedback controller for a single-input single-output nonlinear dynamical system with a full relative degree. While all the previous research works on the output-feedback control are based on dynamic observers, a new state estimator which uses the past values of the measurable system output is proposed. We name it backward-difference state estimator since the derivatives of the output are estimated simply by backward difference of the present and past values of the output. The disturbance generated due to the error between the estimated and real state variables is compensated using an additional robustifying control law whose gain is tuned adaptively. Overall control system guarantees that the tracking error is asymptotically convergent and that all signals involved are uniformly bounded. Theoretical results are illustrated through a simulation example of inverted pendulum.

• Journal of IKEEE
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• v.18 no.2
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• pp.220-227
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• 2014

This paper presents a control method of Single-Inductor Dual-Output DC-DC Converter using Common mode feedback and differential feedback loops. To generate duty used for differential mode feedback loop, this paper propose relative sawtooth circuit using current divider circuit which makes ramp signal with variable dead-time. Two outputs of the Single-Inductor Dual-Output DC-DC Converter are specified for 2.8 V and 4.2 V with input voltage 2.5 V. The maximum conversion efficiency of designed SIDO DC-DC Converter is 95% at total output power of 539mW. Cross regulations of Boost1 and Boost2 are 3.57% and 4% each, when increasing twice times output current.