• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.52-57
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• 2009

This paper presents a low-noise low-dropout linear regulator that is suitable for on-chip integration with RF transceiver ICs. In the bandgap reference, a stacked diode structure is adopted for saving silicon area as well as maintaining low output noise characteristic. Theoretical analysis for supporting the approach is also described. The linear regulator is fabricated in $0.18{\mu}m$ CMOS process. It operates with an input voltage range of 2.2 V - 5 V and provide the output voltage of 1.8 V and the output current up to 90 mA. The measured line and load regulation is 0.04%/V and 0.46%, respectively. The output noise voltage is measured to be 479 nV/$^\surd{Hz}$ and 186 nV/$^\surd{Hz}$ from 100 Hz and 1 kHz offset, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.539-546
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• 2007

In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

• Journal of Biomedical Engineering Research
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• v.21 no.3 s.61
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• pp.255-260
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• 2000

This paper presents a radio-telemetry patient monitor. which is used for intensive cal?e units. emergency and surgical operation rooms to monitor continuously patients' vital signs. The radio-telemetry patient monitor consists of a vital sign acquisition unit. wireless data transmission units and a vital sign-monitoring unit. The vital sign acquisition unit amplifies biological signals, performs analog signal to serial digital data conversion using the one chip micro-controller. The converted digital data is modulated FSK in UHF band using low output power and transmitted to a remote site in door. In comparison with analog modulation. FSK has major advantages to improve performance with respect to noise resistance with fower error and the potential ability to process and Improve quality of the received data. The vital sign-monitoring unit consists of the receiver to demodulate the modulated digital data, the LCD monitor to display vital signs continuously and the thermal head printer to record a signal.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2002.02a
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• pp.192-197
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• 2002

1. 실시간 모니터링 -온실 내부환경의 계측장치로 모듈화된 단일 칩 마이크로프로세서를 이용한 하우스 모니터를 개발하였다. 개발된 다수의 하우스 모니터는 RS-485통신을 이용하여 개발된 프로토콜을 통하여 그룹 모니터와 통신하면서 계측 데이터를 전송하였고 안정된 계측 성능을 보였다. 또한 그룹 모니터는 하우스모니터로부터 수신한 데이터를 인터넷 환경 TCP/IP 통신에 의해 서버에 정보를 전송하고 데이터베이스 서버에 저장할 수 있었다. 2. 클라이언트 서버 모델 -클라이언트 모니터를 통하여 허용된 사용자들은 해당 온실의 상황을 원격지에서 파악할 수 있는 있었다. 또한 분산환경 기술을 이용하여 서버를 경유하여 데이터베이스 서버에서 데이터 셋을 가져와 과거 재배 사례 등을 조회 및 이용 가능하였다. 이는 전문가에게 접근을 허용함으로써 재배에 관한 지원이 가능하도록 하였다. 데이터 베이스 시스템으로 연계하여 온실환경 정보를 분석하는 것이 가능하였다. 3. 기대효과 및 나아가야 할 방향 -개발된 시스템을 식물 공장 내 작물의 재배환경을 데이터베이스화하여 재배사례 데이터베이스를 형성하고 작물이 가장 잘 자라는 최적 재배 환경을 연구하여 고품질의 작물 재배에 이용될 수 있다. 또한 식물공장의 운전실적, 환경 조건, 환경 조절비용 등의 분석에 효율적으로 이용될 수 있을 것으로 예상되며 각 환경인자들과의 관계를 구명하는데 도움을 줄 것이다. 축적된 작물의 재배 사례 데이터베이스를 이용하여 작물 특성 및 재배 연구에 도움을 줄 수 있을 것이다. 제어 장치들의 운영실적을 분석함으로써 제어 시스템의 효율적이고 경제적인 제어가 가능하도록 할 수 있을 것이다. 이들이 모두 완성되면 전문가 및 전문가 시스템으로부터 지원을 받는 지능형 식물공장이 가능할 것이다. 본 연구에서 개발한 계측 모듈 및 데이터베이스 시스템은 실제 농가에 설치된 전용선을 이용하여 실증 실험을 통해 수정·보완하여야 할 것이다. 또한 시설원예분야에서 있어서 통신체계에 대한 표준화 연구가 수행되어 앞으로 개발될 다른 시스템들과의 호환성을 갖도록 해야 할 것이다. 앞으로 온실의 경영 및 관리 데이터베이스를 개발하여 첨단온실의 통합 관리 및 정보 시스템을 구축하여야 할 것이다. 또한, 시설원예의 환경 설계의 기준을 적용할 수 있도록 하여야 할 것이다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.10
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• pp.65-70
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• 2008

We design and fabricate the 94 GHz Coplanar waveguide(CPW)-to-rectangular waveguide transition that is transmits signal smoothly between the CPW, which is a popular transmission line of the planar circuits, and rectangular waveguide for the 94 GHz transceiver system. The proposed transition composed of the unilateral fin-line taper and open type CPW-to-slot-line transition is based on the hard and inflexible sapphire for the flip-chip bonding of the planar MMICs using conventional MMIC technology. We optimize a single section transition to achieve low loss by using an EM field solver of Ansoft's HFSS and fabricate the back- to-back transition that is measured by Anritsu ME7808A Vector Network Analyzer in a frequency range of $85{\sim}105$ GHz. From the measurement and do-embedding CPW with 3 mm length, an insertion and return loss of a single-section transition are 1.7 dB and more an 25 than at 94 GHz, respectively.