• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2219-2228
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• 2000

Caches in a multiprocessing environment introduce the cache coherence problem. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop efficient and reliable verification methods. In this appear we present our experience in using VIS (Verification Interacting with Synthesis), a tool of formal method, to analyze a number of property of a cache coherence protocol, RACE (Remote Access Cache coherent Enforcement).

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.40-46
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• 1999

The task scheduling has an effect on system execution time in a precedence constrained task graph onto the multiprocessor system. This problem is known to be NP-hard. many people made an effort to obtain near optimal schedule. We compared modified critical path schedule with many other methods(CP, MH, DL Swapping) For testing this subject, we created randomly a directed acyclic task graph with many root nodes and terminal nodes simulation result convinced for us that the modified critical path algorithm is superior to the other scheduling algorithm.

• Journal of Korea Society of Industrial Information Systems
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• v.4 no.2
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• pp.44-50
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• 1999

This paper presents a set of techniques to automatically find rate optimal or near rate optimal implementation of shift-invariant flow graphs on pipelined processor, in which pipeline processor has multiple accumulators and internal datapaths. In such case, the problem to be addressed is the scheduling of multiple instruction streams which control all of the pipeline stages. The goal of an automatic scheduler in this context is to rearrange the order of instructions such that they are executed with minimum iteration period between successive iteration of defining flow graphs. The scheduling algorithm described in this paper also focuses on the problem of removing the hazards due to inter-instruction dependencies.

• Journal of Intelligence and Information Systems
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• v.14 no.2
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• pp.83-102
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• 2008

Ubiquitous computing requires timely supply of contextual information in order to upgrade decision quality. In this sense, this study is aimed at proposing a multi-dynamic decision support system for highly ill-structured problems. Especially, it is very important for decision makers in the ubiquitous computing to coordinate conflicts among local goals and global goal harmoniously. The proposed Multi-Dynamic Decision Support System (MDDSS) is basically composed of both central structure and distributed structure, in which central structure supports multi objects decision making and distributed structure supports individual decision making. Its hybrid architecture consists of decision processor, multi-agent controller and intelligent knowledge management processor. Decision processor provides decision support using contexts which come from individual agents. Multi-agent controller coordinates tension among multi agents to resolve conflicts among them. Meanwhile, intelligent knowledge management processor manages knowledge to support decision making such as rules, knowledge, cases and so on. To prove the validity of the proposed MDDSS, we applied it to an u-fulfillment problem system in which many kinds of decision makers exist trying to satisfy their own objectives, and timely adjustment of action strategy is required. Therefore, the u-fulfillment problem is a highly ill-structured problem. We proved its effectiveness with the aid of multi-agent simulation comprising 60 customers and 10 vehicles under three experimental modes.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.40-42
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• 2001

캐쉬 일관성 프로토콜의 하나인 MESI 프로토콜은 다중 프로세싱 환경에서 각각의 프로세서와 메모리 사이의 데이터 일관성을 유지하기 위해 캐쉬, 메모리 등의 통신 개체들을 조정하는 일종의 규칙들 중 하나이다. 프로세서의 수가 많아지고 시스템이 복잡해 질 경우 MESI 프로토콜을 정확하게 설계하고 그 동작을 분석하기는 매우 어렵다. 본 연구에서는 정형기법 도구인 ESTEREL을 이용하여 MESI 프로토콜을 설계하고 그 동작의 안정성을 검증하여, 시스템의 정확성과 안정성을 보장하는 방법에 대해 논한다.

• Journal of KIISE:Software and Applications
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• v.29 no.11
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• pp.826-836
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• 2002

We need an enormous amount of memories for name spaces as well as additional processors if we are to effectively exploit a massively parallelism in nested loops of functional languages such as Id. If there is no sufficient amount of memories enough to exploit that parallelism, the execution of programs can be aborted during the unfolding of loops. Additionally, if loops are overunfolded, compared with the number of processors available, the system performance can be degraded severely due to the overhead of loop unfolding. This paper suggests and analyzes an algorithm which can be used to effectively unfold nested loops of functional languages on multithreaded architectures. This algorithm has a feature to unfold a given nested loop safely and near optimally, considering the system resources of processors and memories available when the loop is to be unfolded.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.243-252
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• 2005

This paper introduces a noble modeling technique to build data communication prediction models in multiprocessors, using Least-Squares and Robust Estimation methods. A set of sample communication rates are collected by using a few small input data sets into workload programs. By applying estimation methods to these samples, we can build analytic models that precisely estimate communication rates for huge input data sets. The primary advantage is that, since the models depend only on data set size not on the specifications of target systems or workloads, they can be utilized to various systems and applications. In addition, the fact that the algorithmic behavioral characteristics of workloads are reflected into the models entitles them to model diverse other performance metrics. In this paper, we built models for cache miss rates which are the main causes of data communication in shared memory multiprocessor systems. The results present excellent prediction error rates; below $1\%$ for five cases out of 12, and about $3\%$ for the rest cases.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.453-457
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• 2000

병렬 시스템 환경에서 최적의 스케쥴링을 수행하기 위해서는 병렬성을 가진 iteration 들에 대해 최소의 동기화 오버헤드와 load balance 가 달성하도록 스케쥴링을 수행해야한다. 다중 프로세서들은 실행을 위하여 메모리로부터 iteration 들에 대한 chunk를 계산한 후 할당받게 된다. 이때, 각 프로세서들의 상호 배타적인 메모리 접근으로 많은 오버헤드 및 병목현상이 발생된다. 또한, 프로세서에게 할당된 chunk 내 iteration 들의 실행시간 분포가 서로 상이한 경우에는 load imbalance 의 원인이 되어 결과적으로 전체 스케쥴링에 나쁜 영향을 준다. 따라서, 최적의 스케쥴링을 수행하기 위해서 본 논문에서는 기존의 스케쥴링 방법들에서 문제점들을 도출하고 자료의 국부성과 프로세서 동족성을 고려한 개선된 병렬 루프 알고리즘을 제안하고, 성능평가를 통해 개선된 알고리즘이라는 것을 보였다.

• Journal of Korea Multimedia Society
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• v.16 no.8
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• pp.914-926
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• 2013

Among the recent security systems, security system with fingerprint recognition gets many people's interests through the strengths such as exclusiveness, convenience, etc, in comparison with other security systems. The most important matters for fingerprint recognition system are reliability of matching between the fingerprint in database and user's fingerprint and rapid process of image processing algorithms used for fingerprint recognition. The existing fingerprint recognition system reduces the processing time by removing some processes in the feature extraction algorithms but has weakness of a reliability. This paper realizes the fingerprint recognition algorithm using MAMS(Multi-Access Memory System) for both the rapid processing time and the reliability in feature extraction and matching accuracy. Reliability of this process is verified by the correlation between serial processor's results and MAMS-PP64's results. The performance of the method using MAMS-PP64 is 1.56 times faster than compared serial processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.