• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.7
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• pp.144-149
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• 2002

This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.2
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• pp.137-140
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• 2004

다중 프로세서 시스템이 개발됨에 따라, 새로운 일정계획문제, 하나의 작업이 하나이상의 기계에 의해 동시에 처리되어야 하는 문제가 대두되었다. 이 연구에서는 선행관계를 가진 이러한 다중 프로세서 일정계획문제에 대해 다루어 보았다. 이 연구의 목적은 makespan을 최소화하는 일정계획을 찾는 것이다. 일반적으로 Branch and Bound 기법을 이용하여 선행관계를 가진 다중 프로세서 일정계획문제의 최적해를 찾았는데, 해의 탐색시간이 너무 오래 걸린다는 단점이 있었다. 본 연구에서는 짧은 시간 내에 최적해와 가까운 근사해를 simulated annealing(SA)방법을 이용하여 구해보았다. SA의 성능을 측정하기 위하여, SA의 CPU 처리시간과 구한 근사해를 40개의 예제문제를 통하여 Kramer의 방법의 CPU 처리시간과 최적해와 비교해 보았다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.10
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• pp.848-860
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• 2000

본 논문에서는 한 번에 여러 개의 명령어를 이슈할 수 있는 다중 이슈 프로세서(in-order, multiple-issue processors)에 대해 최악 실행시간을 분석하는 기법을 제시한다. 명령어들의 이슈 형태를 분석하기 위해서 명령어들 사이의 의존성 간계를 표현하는 IDG(Instruction Dependence Graph)라고 하는 자료구조를 사용한다. 이 자료구조로부터 각 명령어들의 이슈간 거리 범위를 구하고, 프로그램의 계층적인 분석 과정에서 점차로 더 정확한 이슈간 거리 범위로 갱신한다. 프로그램의 최악 실행시간은 최종적으로 얻어진 프로그램 전체에 대한 IDG를 분석하여 얻은 명령어들의 이슈간 거리 범위로부터 계산한다. 제안하는 기법을 구현한 시간 분석기를 사용하여 실험한 결과, 논문에서 사용한 다중 이슈 프로세서 모델에 대해서 정확하게 다중 이슈 형태를 분석할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.101-108
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• 2007

Parallel processing algorithms, coupled with advanced networking and distributed computing architectures, improve the overall computational performance, dependability, and versatility of a digital signal processing system In this paper, novel parallel algorithms are introduced and investigated for advanced sonar algorithm, conventional matched-field processing (CMFP). Based on a specific domain, each parallel algorithm decomposes the sequential workload in order to obtain scalable parallel speedup. Depending on the processing requirement of the algorithm, the computational performance of the parallel algorithm reveals different characteristics. The high-complexity algorithm, CMFP shows scalable parallel performance on the array of DSP processors. The impact on parallel performance due to workload balancing, communication scheme, algorithm complexity, processor speed, network performance, and testbed configuration is explored.

• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.199-206
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• 2004

Under the multiprogrammed situation, the performance of multiprocessor system is affected by the process allocation policy of the operating systems. The lowest communication cost can be achieved when the related processes positioned to the adjacent processors. While the effective allocation is quite difficult to the real situation, and the processing of the allocation policy consumes some computation time. The dual-ring CC-NUMA systems exhibit a quite performance difference according to the process a1location policy due to a lot of unbalanced memory transactions on the interconnection networks. In this paper, I propose a load balanced dual-link CC-NUMA system that does not requires the processes allocation policy. By the program-driven simulation results. the proposed system shows no remarkable difference according to the allocation policy while the dual-ring systems shows 10％ performance improvement by the process allocation. In addition, the proposed system outperforms the dual~ring systems about 1.5 times.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.177-187
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• 2000

In the past several years, many systems which adopted ring topology with high-speed unidirectional point-to-point links have emerged to overcome the limit of bus for interconnection network of clustered multiprocessor system. However, rapid increase of processor speed and performance improvement of local bus and memory system limit scalability of system with point-to-point link of standard bandwidth. Therefore, necessity to extend bandwidth is emphasized. In this paper, we adopt PANDA system as base model, which is clustering-based multiprocessor system. By simulating a model adopting commercial processor and local bus specification, we show that point-to-point link is bottleneck of system performance, and bandwidth expansion by more than 200% is needed. To expand bandwidth of interconnection network, it needs excessive design cost and time to develop new point-to-point link with doubled bandwidth. As an alternative to double bandwidth, we propose several ways to implement dual ring -simple dual ring, transaction-separated dual ring, direction-separated dual ring- by using off-the-shelf point-to-point links with IEEE standard bandwidth. We analyze pros. and cons. of each model compared with doubled-bandwidth single ring by simulation.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.147-162
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• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.135-148
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• 2000

In this paper, we present a linear scheduling method for homogeneous multiprocessor systems using genetic algorithms. In general, genetic algorithms randomly generate initial strings, which leads to long operation time and slow convergence due to an inappropriate initialization. The proposed algorithm considers communication costs among processors and generates initial strings such that successive nodes are grouped into the same cluster. In the crossover and mutation operations, the algorithm maintains linearity in scheduling by associating a node with its immediate successor or predecessor. Linear scheduling can fully utilize the inherent parallelism of a given program and has been proven to be superior to nonlinear scheduling on a coarse grain DAG (directed acyclic graph). This paper emphasizes the usability of the genetic algorithm for real-time applications. Simulation results show that the proposed algorithm rapidly converges within 50 generations in most DAGs.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.499-510
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• 2004

This paper proposes a heuristic load balancing algorithm for multiprocessor systems. The algorithm minimizes the number of idle links to distribute load traffic and reduces its communication cost. Each processor iteratively tries to transfer unit load to/from every neighbor processors. However, real load transfer is collectively done after complete load traffic calculation to minimize useless traffic. The proposed algorithm can be employed in various interconnection topologies with slight modifications. In this paper, it is applied to both hypercube and mesh environments. For performance evaluation, simulation studies are performed. The performance of proposed algorithm is compared to those of two well-known algorithms. The results show that the proposed algorithm always balances the loads perfectly. Furthermore, it reduces the communication costs by $70{\%}{\~}90{\%}$ in the hypercube ; and it reduces the cost by $\75{\%}$ in the mesh, compared to existing algorithms.