한국정보과학회논문지:시스템및이론 (Journal of KIISE:Computer Systems and Theory)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
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다중 이슈 프로세서를 위한 최악 실행시간 분석 기법

A Worst Case Execution Timing Analysis Technique for Multiple-Issue Processors

  • 임성수 (서울대학교 컴퓨터공학과) ;
  • 한정희 (미시간주립대학교 전기컴퓨터공학과) ;
  • 김지홍 (서울대학교 컴퓨터공학부) ;
  • 민상렬 (서울대학교 컴퓨터공학부)
  • 발행 : 2000.10.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 한 번에 여러 개의 명령어를 이슈할 수 있는 다중 이슈 프로세서(in-order, multiple-issue processors)에 대해 최악 실행시간을 분석하는 기법을 제시한다. 명령어들의 이슈 형태를 분석하기 위해서 명령어들 사이의 의존성 간계를 표현하는 IDG(Instruction Dependence Graph)라고 하는 자료구조를 사용한다. 이 자료구조로부터 각 명령어들의 이슈간 거리 범위를 구하고, 프로그램의 계층적인 분석 과정에서 점차로 더 정확한 이슈간 거리 범위로 갱신한다. 프로그램의 최악 실행시간은 최종적으로 얻어진 프로그램 전체에 대한 IDG를 분석하여 얻은 명령어들의 이슈간 거리 범위로부터 계산한다. 제안하는 기법을 구현한 시간 분석기를 사용하여 실험한 결과, 논문에서 사용한 다중 이슈 프로세서 모델에 대해서 정확하게 다중 이슈 형태를 분석할 수 있었다.

키워드

참고문헌

  1. R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding Worst Case Instruction Cache Performance. In Proceedings of the 15th Real-Time Systems Symposium, pages 172--181, Dec. 1994 https://doi.org/10.1109/REAL.1994.342718
  2. J.-Y. Choi, I. Lee, and I. Kang. Timing Analysis of Superscalar Processor Programs Using ACSR. In Proceeding of the 11th Workshop on Real-Time Operating Systems and Software, pages 63--67, May 1994 https://doi.org/10.1109/RTOSS.1994.292559
  3. T. A. Diep and J. P. Shen. VMW: A Visualization-Based Microarchitecture Workbench. IEEE Computer, 28(12):57--64, Dec. 1995 https://doi.org/10.1109/2.476200
  4. C. Ferdinand, F. Martin, and R. Wilhelm. Applying Compiler Techniques to Cache Behavior Prediction. In Proceedings of 1997 ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems, Pages 37-46, June 1997
  5. E. Harcourt, J. Mauney, and T. Cook. High-Level Timing Specification of Instruction-Level Parallel Processors. Tehnical Report TR?3?8, Dept. of Computer Science, North Carlina State University, August 1993
  6. M. Harmon, T. P. Baker, and D. B. Whalley. A Retargetable Technique for Predicting Execution Time. In Proceedings of the 13th Real-Time Systems Symposium, pages 68-77, Dec. 1992 https://doi.org/10.1109/REAL.1992.242675
  7. C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon . Bounding Pipeline and Instruction Cache Performance. IEEE Transactions on Computers, 48(1):53-70, Jan. 1999 https://doi.org/10.1109/12.743411
  8. C. A. Healy, D. B. Whalley. and M. G. Harmon. Integrating the Timing Analysis of Pipelining and Instruction Caching, In Proceedings of the 16th Real-Time Systems Symposium, pages 288-297, December 1995
  9. M. Johnson. Superscalar Microprocessor Design. Prentice Hall. Englewood Cliffs, NJ. 1991
  10. Y. S. Li, S. Mailk, and A. Wolfe. Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. In Proceedings of the 16th Real-Time Software. In Proceedings of the 16th Real-Time Systems Symposium, pages 298-307, Dec. 1995
  11. S.-S. Lim, Y. H. Bae, G. T. Jang, B,-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, and C. S. Kim. An Accurate Worst Case Timing Analysis for RISC Processors. IEEE Transactions On Software Engineering, 21(7):593-604, July 1995 https://doi.org/10.1109/32.392980
  12. A. Mok. Evaluating Tight Execution Time Bounds of Programs by Annotations. In Proceedings of the 10th IEEE Workshop on Real-Time Operating Systems and Software, pages 74-80, 1989
  13. K. Naresimhan and K. Nilsen. Portable Execution Time Analysis for RISC Processors. In Proceedings of the Workshop On Architecture for Real-Time Systems, April 1994
  14. G. Ottosson and M. Sjodin. Worst-Case Execution Time Analysis for Modern Hardwre Architectures. In Proceedings of 1997 ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems, pages 47-55, June 1997
  15. P. Puschner and C. Koza. Calculating the Maximum Execution Time of Real-Time Programs. Real-Time Systems, 1(2):159-176, Sept. 1989 https://doi.org/10.1007/BF00571421
  16. A. C. Shaw. Reasoning About Time in Higher-Level Language Software. IEEE Transactions on Software Engineering, 15(7):875-889, July. 1989 https://doi.org/10.1109/32.29487
  17. H. Theiling and C. Ferdinand. Combining Abstract Interpretation and ILP for Microarchi tecture Modelling and Program Path Analysis. In Proceedings of the 19th IEEE Real-Time Systems Symposium, pages 144-153, Dec. 1998
  18. N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst-Case Execution Times. Real-Time Systems, 5(4):319-343, Oct. 1993 https://doi.org/10.1007/BF01088834