• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.5
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• pp.296-303
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• 2014

Reference Broadcast Synchronization (RBS) is one of the most prominent synchronization protocols in wireless sensor nework. Given that the broadcasting medium is available, RBS can give very high accuracy of synchronization. However, RBS uses instantaneous synchronization and results in time discontinuity, which might cause serious faults in the distributed system. Also, RBS lacks packet loss tolerance, which brings about degraded performance in severe conditions of wireless channel. In this paper, the problem of time discontinuity in RBS is pointed out and the effect of packet loss on the performance of RBS is examined. Then, a continuous synchronization and a packet loss tolerance mechanism for RBS are proposed, and the result is verified through simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The KIPS Transactions:PartC
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• v.19C no.3
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• pp.209-214
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• 2012

Time synchronization is important role in a network, especially in Wireless Sensor Network (WSN) which is required for time-critical applications such as surveillance, tracking, data fusion and scheduling. Time synchronization in WSN should meet the other different requirements than the one in other networks because WSN has critical resource constraints, especially power consumption. This paper presents a new time synchronization scheme for WSN, which is energy efficient by reducing communication overhead. Simulation test shows this new scheme has better energy efficiency and performance of accuracy than existing schemes proposed previously.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.51-56
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• 2009

Time synchronization algorithm in wireless sensor networks is essential to various applications such as object tracking, data encryption, duplicate detection, and precise TDMA scheduling. This paper describes CDRS that is a time synchronization algorithm using the Clock Drift rate and Reference Signals between two sensor nodes. CDRS is composed of two steps. At first step, the time correction is calculated using offset and the clock drift rate between the two nodes based on the LTS method. Two nodes become a synchronized state and the time variance can be compensated by the clock drift rate. At second step, the synchronization node transmits reference signals periodically. This reference signals are used to calculate the time difference between nodes. When this value exceeds the maximum error tolerance, the first step is performed again for resynchronization. The simulation results on the performance analysis show that the time accuracy of the proposed algorithm is improved, and the energy consumption is reduced 2.5 times compared to the time synchronization algorithm with only LTS, because CDRS reduces the number of message about 50% compared to LTS and reference signals do not use the data space for timestamp.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.11a
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• pp.30-34
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• 2001

본 논문에서는 근거리에 놓여있는 노트북, 휴대폰, PDA, 혜드셋 등 각종 이동 가능한 장치들을 하나의 무선네트워크로 연결할 수 있는 블루투스의 베이스밴드 시스템 프로토콜 기능을 분석하고 설계하였다. 즉, 전체적인 논리 기능구조를 설계한 후 하드웨어로 구현될 패킷생성 블록, HEC와 CRC 기능블륵, Whitening/Dewhitening 기능블록, FEC 기능블록, 입출력 블록(TX, RX 루틴), 클럭 생성 기능블록, 주파수 선별 기능블록, 오디오 기능블록 그리고, 패킷 제어 블록들의 처리절차를 Verilog HDL 코드로 설계 및 검증하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.319-321
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• 2004

최근 이더넷(Ethernet) 보급과 사용자의 증가 그리고 다양한 응용 서비스들의 등장으로 인하여 점차 네트워크 트래픽이 폭증하고 있다. 이에 따라서 SLA(Service Level Agreement)를 위한 대역폭 조절(Bandwidth의 Regulation)의 중요성은 더욱 높아지고 있다. 그러나 기존에 제시된 대역폭 조절 방식들은 이더넷에 적합하지 않거나 또는 너무 복잡하여, EFM(Ethernet for First Mile)에 적용하기 어려웠다. 그래서 본 논문에서는 이더넷에 적용하기 적합한 간단하면서도 효과적인 대역폭 조절(Bandwidth Regulation) 방법인 속도 계산(Rate Calculation)방식을 제안하며, 제안한 메커니즘에 대한 시뮬레이션을 통한 성능 분석을 수행하였다.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.216-223
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• 2005

A computer clock has limits in accuracy and precision affected by its inherent instability, the environment elements, the modification of users, and errors of the system. So the computer clock needs to be synchronized with a standard clock if the computer system requires the precise time processing. The purpose of synchronizing clocks is to provide a global time base throughout a distributed system. Once this time base exists, transactions among members of distributed system can be controlled based on time. This paper discusses the integrated approach to clock synchronization. An embedded system is considered for time synchronization based on the GPS(Global Positioning System) referenced time distribution model. The system uses GPS as standard reference time source and offers UTC(Universal Time Coordinated) through NTP(Network Time Protocol). A clock model is designed and adapted to keep stable time and to provide accurate standard time with precise resolution. Private MIB(Management Information Base) is defined for network management. Implementation results and performance analysis are also presented.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.1-10
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• 2007

This paper describes the development of a network-based passenger information system(PIS) which provides the convenience of the passenger of the train and heightens the effect of the subtitle service, the advertising and the shelter guidance broadcasting against the urgent event. The existing system uses VGA signal distributor in order to broadcast information with image and subtitle and voice guidance. In this paper we improve the existing system by applying the UDP and TCP/IP protocol and use a reference clock to solve a data loss and synchronization problem which occurs in this case. We also developed an XML-based subtitle authoring tool which can edit and play the subtitles with various 3D to improve the automatic guidance broadcasting and advertisement effect according to the operation schedule of the train. The system performance was evaluated through a simulation.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.1-5
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• 2011

We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.