• 산업기술연구
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• 제29권B호
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• pp.101-105
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• 2009

A 1.571GHz LC VCO with optimized spiral inductor for GPS receiver is designed in 130nm CMOS process. The phase noise of the VCO has been reduced the use of high Q inductor and on chip filter. It has phase noise of -91dBc/Hz, -111dBc/Hz, and -131dBc/Hz at 10kHz, 100kHz, and 1MHz offset frequencies from the carrier, respectively. This VCO consumes 2mA from a 0.6V supply.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2007년도 학술대회
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• pp.436-439
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• 2007

This paper describes the optimization of PGS(Patterned Ground Shield) of 5.5 turns rectangular spiral inductor using Taguchi's method. PGS is decrease method of parasite component by silicon substrate among dielectric loss reduction method. By using the taguchi's method, each parameter is fixed upon that PGS high poison(A), slot spacing(B), strip width(C) and overlap turn number(D) of PGS design parameter. Then we verified that percentage contribution and design sensitivity analysis of each parameter and level by signal to noise ratio of larger-the-better type. We consider percentage contribution and design sensitivity of each parameter and level, and then verify that model of optimization for PGS is lower inductance decreasing ratio and higher Q-factor increasing ratio by EM simulation.

• 전자공학회논문지D
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• 제34D권9호
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• pp.21-27
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• 1997

Square spiral inductors are designed with EM program in accordance with the inner diameter and the metal thickness which is 0.2.mu.m and 20.mu.m respectively. We propose a parameter extraction method based on the S-parameter. Lumped equivalent circuits of spiral inductors are analyed with reflection coefficient S$_{11}$, of witch freqency rnage is 1~10GHz. When metal thickness is 0.2.mu.m, S$_{11}$ with EM simulation is not the same as S$_{11}$ that of SPICE simulation. So we suggests a new lumped equivalent circuits which compensate circuits. Te new lumped equivalent circuits are adequate for other inductor with small scale at high frequencies.ncies.

• 전기학회논문지
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• 제58권2호
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• pp.363-368
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• 2009

In the paper, we confirmed improvement Noise figure of the entire RF front-end using spiral inductor with PGS(Patterned Ground Shield) and current bleeding techniques. LNA design is to achieve simultaneous noise and input matching. Spiral inductor in input circuit of LNA inserted PGS for betterment of Q-factor. we modeling inductor using EM simulator, so compared with inductor of TSMC 0.18um. We designed and simulation the optimum structure of PGS using Taguchi's method. We confirmed enhancement of noise figure at LNA after substituted for inductor with PGS. Mixer designed using current bleeding techniques for reduced noise. We designed LNA using inductor with PGS and Mixer using current bleeding techniques, so confirmed improvement of noise figure.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.272-273
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• 2007

This paper presents the characteristic of rectangular and octagonal spiral inductor using PGS(Patterned Ground Shield). We investigated variation of inductance and Q-factor with changing of turn number at fixed width, spacing and inner diameter. We confirmed that characteristic of inductance and Q-factor be appled PGS in rectangular and octagonal types spiral inductor by EM simulation tool. Inductance decreased irrespective of structure but Q-factor increased. When PGS not exist, Q-factor of Inductor is analogous at classification frequency but, rectangular is a few larger then octagonal in small turn number. The other side, When PGS is inserted, we confirmed that octagonal lager then rectangular in many turn number. Q-factor is improved in case of octagonal structure and small turn number by PGS effect.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.645-648
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• 1998

We used a three-dimensional inductance extraction program, Fasthenry for optimal design of the spiral inductors on silicon substrate. The inductance and quality factor of the spiral inductors with various design parameters were calculated so that the optimal parameter value was determined. The spiral inductors then were fabricated using different foundary processes and were measured using the network analyzer and microwave probes. The pad and other parasitics of measurement system were de-embedded using the y-parameter calibration technique. the inductors fabricated using the LG 0.8um process and HP 0.5um process showed the quality factor of 5.8 and 3, respectively. Finally the equivalent circuit farameters of the spiral inductors on silicon substrate were extracted from the measurement data using the matlab.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.669-672
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• 2003

With the advances on wireless internet technology, many research on minimization of wireless LAN is on the progress. To apply passive components in MCM, characteristic analysis of passive components is essential. In this paper, three square spiral inductors were modeled by HSPICE using PEEC (Partial Element Equivalent Circuit) method. Afterwards, Monte-Carlo analysis was performed to evaluate the optimized parameters. This work will give an idea on PEEC modeling of spiral inductor, and enable researchers with predictive data before large scale manufacturing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.890-893
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• 2004

In this study, Spiral inductors on the $SiO_2/Si$(100) substrate were fabricated by the magnetron sputtering method. Cu thin film with the thickness of 2 ${\mu}m$ was deposited on the substrate. Also we fabricated square inductors through the wet chemical etching technique. The inductors are completely specified by the turn width and the spacing between spirals. Both the width and spacing between spirals were varied from 10 to 60${\mu}m$ and from 20 to 70 ${\mu}m$, respectively. Inductance and Q factor dependent on the frequency were investigated to analyze performance of spiral inductors.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.