• Korean Journal of Materials Research
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• v.13 no.6
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• pp.404-408
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• 2003

SiC nanorods have been grown on Si (100) substrate directly. Tetramethylsilane and Ni were used for SiC nanorod growth. After 3minute, SiC nanorod had grown by CVD. Growth regions ware divided by two regions with diameter. The First region consisted of thin SiC nanorods having below 10 nm diameter, but second region's diameter was 10∼50 nm. This appearance shows by reduction of growth rate. The effect of temperature and growth time was investigated by scanning electron microscopy. Growth temperature and time affected nanorod's diameter and morphology. With increasing growth time, nanorod's diameter increased because of the deactivation effect. But growth temperatures affected little. By TEM characterization, grown SiC nanorods consisted of the polycrystalline grain.

• Korean Journal of Materials Research
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• v.16 no.1
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• pp.37-43
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• 2006

Carbon nanotube cathodes (CNT cathodes) were fabricated by a screen printing method using multi-walled carbon nanotubes. The effects of surface treatment on CNT cathodes were investigated for use in high efficiency field emission displays. The optimum surface treatment for a CNT cathode is dependent on a relative bonding force of CNT films on the cathode after a heat treatment. Because of the high bonding force used in the Liquid method, this method is recommended for CNT cathodes which are heat-treated at $390^{\circ}C$ in a $N_2$ atmosphere. The Rolling method is applicable for CNT cathodes fabricated at $350^{\circ}C$ in an atmosphere of air. The results of this study provide basic criteria for the selection of an appropriate surface treatment for large area CNT cathodes.

• Korean Journal of Materials Research
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• v.13 no.9
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• pp.593-597
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• 2003

Anodic aluminum oxide (AAO) membrane was made of aluminum sheet (99.6%, 0.2 mm thickness). The regular array of hexagonal nano pores or channels were prepared by two step anodization process. A detail description of the AAO fabrication is presented. After the 1st anodization in oxalic acid (0.3 M) at 45 V, The formed AAO was removed by etching in a solution of 6 wt% $H_3$$PO_4$＋1.8 wt% $H_2$$CrO_4$. The regular arrangement of the pores was obtained by the 2nd anodization, which was carried out in the same condition as the 1st anodization. Subsequently, the alumina barrier layer at the bottom of the channel layer was removed in phosphoric acid (1M) after removing of aluminum. Pore diameter, density, and thickness could be controlled by the anodization process parameters such as applied voltage, anodizing time, pore widening time, etc. The pore diameter is proportional to the applied voltage and pore widening time. The pore density and thickness can be controlled by anodization temperature and voltage.

• Korean Journal of Materials Research
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• v.25 no.4
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• pp.209-213
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• 2015

Synthesis of nano-silica using water glass in a Sol-Gel process is one of several methods to manufacture nano-silica. In nano-silica synthesized from water glass, there are various metal impurities. However, synthesis of nano-silica using water glass in a Sol-Gel process is an interesting method because it is relatively simple and cheap. In this study, nano-silica was synthesized from water glass; we investigated the effect of pH on the synthesis of nano-silica. The morphology of the nanosilica with pH 2 was flat, but the surface of the nano-silica with pH 10 had holes similar to small craters. As a result of ICP-OES analysis, the amount of Na in the nano-silica with pH 2 was found to be 170 mg/kg. On the other hand, the amount of Na in the nano-silica with pH 10 was found to be 56,930 mg/kg. After calcination, the crystal structure of the nano-silica with pH 2 was amorphous. The crystal structure of the nano-silica with pH 10 transformed from amorphous to tridymite. This is because elemental Na in the nano-silica had the effect of decreasing the phase transformation temperature.

• Korean Journal of Materials Research
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• v.25 no.5
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• pp.238-246
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• 2015

$H_2S$ is a flammable toxic gas that can be produced in plants, mines, and industries and is especially fatal to human body. In this study, CuO nanowire structure with high porosity was fabricated by deposition of copper on highly porous singlewall carbon nanotube (SWCNT) template followed by oxidation. The SWCNT template was formed on alumina substrates by the arc-discharge method. The oxidation temperatures for Cu nanowires were varied from 400 to $800^{\circ}C$. The morphology and sensing properties of the CuO nanowire sensor were characterized by FESEM, Raman spectroscopy, XPS, XRD, and currentvoltage examination. The $H_2S$ gas sensing properties were carried out at different operating temperatures using dry air as the carrier gas. The CuO nanowire structure oxidized at $800^{\circ}C$ showed the highest response at the lowest operating temperature of $150^{\circ}C$. The optimum operating temperature was shifted to higher temperature to $300^{\circ}C$ as the oxidation temperature was lowered. The results were discussed based on the mechanisms of the reaction with ionosorbed oxygen and the CuS formation reaction on the surface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.862-867
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• 2006

Bi-based nano-varistors and micro-varistors fabricated with each ZnO nano-powder and micro-powder were studied about characteristics on the surge capability in this study. ZnO nano-varistors were sintered in air at $1050^{\circ}C$ for 2 hr. The voltage-current and residual voltage properties of ZnO nano-varistor were compared with their of ZnO micrio-varistor. As a result of these properties, our ZnO nano-varistor has about 3 times at operating voltage as compared with conventional ZnO varistor fabricated with micro-powder and the residual voltage was 8.06 kV at nominal discharge current 101kA in the lighting impulse current test. And then the residual voltage rate 1.72 of our nano-varistor has had better performance than the 1.79 of micro-varistor because ZnO nano-varistor has shown much quick response property because of increasing effective cross-section area. Also, to analysis surge capability took thermal images for pyrexia temperature distribution with each of the varistors after operating varistors. Nano-varistor doesn't have shown local overheating and can confirm accurate temperature grade on the surface of its.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1005-1009
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• 2006

High quality three-dimensional (3D) heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate to improve the efficiency of tarrier transport. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources (As2, As4) were varied to calibrate the selective area growth conditions and the 3D GaAs-AlGaAs heterostructures were fabricated into the ridge type and the V-groove type. Scanning micro-photoluminescence $({\mu}-PL)$ measurements and the following analysis revealed that the gradually (adiabatically) coupled 1D-2DEG (electron gas) field effect transistor (FET) system was successfully realized. These 3D-heterostructures are expected to be useful for the realization of high-performance mesoscopic electronic devices and circuits since it makes it possible to form direct ohmic contact onto the (quasi) 1D electron channel.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1000-1004
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• 2006

In this paper, thermal stability of Ni-silicide formed on the SOI substrate with $B_{11}$ has been characterized. The sheet resistance of Ni-silicide on un-doped SOI and $B_{11}$ implanted bulk substrate was increased after the post-silicidation annealing at $700^{\circ}C$ for 30 min. However, in case of $B_{11}$ implanted SOI substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min. The main reason of the excellent property of $B_{11}$ sample is believed to be the retardation of Ni diffusion by the boron and bottom oxide layer of SOI. Therefore, retardation of Ni diffusion is highly desirable lot high performance Ni silicide technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1037-1043
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• 2006

We report the enhancement of hole injection using ozone-treated Ag nanodots dispersed on indium tin oxide anode in $Ir(ppy)_3-doped$ phosphorescent OLED. Phosphorescent OLED fabricated on Ag nanodots dispersed ITO anode showed a lower turn on voltage and higher luminescence than those of OLEDS prepared commercial ITO anode. Synchrotron x-ray scattering examination results showed that the Ag nanodots dispersed on ITO anode is amorphous structure due to low deposition temperature. It was thought that decrease of the energy barrier height as Ag nanodots changed to $AgO_x$ nanodots by surface treatment using ozone for 10 min led to enhancement of hole injection in phosphorescent OLED. Futhermore, efficient hole injection can be explained by increase of contact region between anode material and organic material through introduction of $Ag_2O$ nanodots.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1001-1006
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• 2005

A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.