• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1880-1884
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• 2004

To analyze the fluid flow and thermal characteristics in a nanoscale system, the planar Poiseuille flow of a Lennar-Jones liquid through parallel plates formed by fixed atoms is studied using nonequilibrium molecular dynamics simulations. The role of important simulation parameters such as the channel width, the magnitude of external field, the temperatures of the top and bottom plates, and the interaction potential parameter between fluid and wall atoms, which affect flow patterns and heat transfer rate inside the channel, are investigated. Under the various simulation conditions, interesting phenomena deviated from the continuum predictions have found.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• Journal of the KSME
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• v.57 no.10
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• pp.38-42
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• 2017

이 글에서는 나노 스케일의 채널이 갖는 특성으로부터 기인하는 이온 및 물질의 전달현상을 이해하기 위한 수치 해석적 연구를 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.429-434
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• 2017

A molecular-continuum hybrid method was developed to simulate microscale and nanoscale fluids where continuum fluidics cannot be used to predict Couette flow. Molecular dynamics simulation is used near the solid surface where the flow cannot be predicted by continuum fluidics, and Navier-Stokes equations are used in the other regions. Numerical simulation of Couette flow was performed using the hybrid method to investigate the effect of solid-liquid interaction and surface roughness in a nanochannel. It was found that the solid-liquid interaction and surface roughness influence the boundary condition. When the surface energy is low, slippage occurs near the solid surface, and the magnitude of slippage decreases with increase in surface energy. When the surface energy is high, a locking boundary condition is formed. The roughness disturbs slippage near the solid surface and promotes the locking boundary condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1885-1890
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• 2013

In this paper, the electrical properties of nanoscale junctionless p-channel MuGFET at cryogenic temperature have been analyzed experimentally. The experiment was performed using a cryogenic probe station which uses the liquid Helium. It has been observed that the drain current oscillation at low drain voltage and cryogenic temperature was more pronounced in junctionless transistor than in accumulation mode transistor. The reason for more marked oscillation is due to the smaller electrical cross section area of the inversion channel which is formed at the center of silicon film in junctionless transistor. It was also observed that the drain current and maximum transconductance were increased as the measurement temperature increased. This is resulted from the increase of hole mobility and the decrease of the threshold voltage as the measurement temperature increases. The drain current oscillation due to the quantum effects can be occurred up to the room temperature when the device size scales down to the nanometer level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.1-7
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• 2008

In this work, a two dimensional, self-consistent Poisson-$Schr{\ddot{o}}dinger$ solver has been implemented to study C-V characteristics in nanometer scale MuGFETs with considering quantum effects. The quantum-mechanical effects on gate-channel capacitance for different device dimension and gate configurations of nanometer scale MuGFETs have been analyzed. It has been found that 4he gate-channel capacitance per unit gate area is increased as the device dimension decreases. For different gate configurations, the gate-channel capacitance is decreased with increase of effective gate number. Those resu1ts have been explained by the distribution profile of electron concentration in the silicon surface and inversion capacitance. The length of inversion-layer centroid has been calculated from inversion capacitance with device dimension and gate configurations.

• Membrane Journal
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• v.26 no.6
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• pp.421-431
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• 2016

Novel membrane technologies that harness ordered nanostructures have recently received much attention because they allow for high permeability due to their reduced flow resistance while also maintaining high selectivity due to their isoporous characteristics. In particular, the opaline structure (made from the self-assembly of colloidal particles) and its inverted form (inverse-opal) have shown strong potential for membrane applications on account of several advantages in processing and the resulting membrane properties. These include controllability over the pore size and surface functional moieties, which enable a wide range of applications ranging from size-exclusive separation to catalytically-reactive membranes. Furthermore, when combined with multiscale architecturing strategies, inverse-opal-structured membranes can be designed to have specific pores or channel structures. These materials are anticipated to be utilized for next-generation, high-performance, and high-value-added functional membranes. In this review article, various types of inverse-opal-structured membranes are reviewed and their functionalization through hierarchical structuring will be comprehensively investigated and discussed.