• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1216-1224
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• 2003

In this paper Dual Band Log-Periodic Dipole Antenna(DLPDA), which can be used at the Cellular/IMT-2000 band, is proposed. The proposed antenna is composed of 2 of Log-Periodic Dipole Antenna(LPDA) and parasitic elements. To investigate the reliability of the proposed antenna, DLPDA is designed at the cellular/IMT-2000 band and analyzed by using the method of moment, Numerical results are compared with measured results. It is shown that although the antenna length is 70 cm, its radiation characteristics satisfied the design goals of gain, VSWR and beamwidth at the Cellular/IMT-2000 band. From these results, the proposed DLPDA is confirmed as the dual band antenna which can be used at the cellular/IMT-2000 band.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.128-132
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• 2008

This paper presents a filter design technique with the embedded passive elements using the low temperature co-fired ceramic (LTCC) process. For the high performance and size reduction, the parasitic elements of the proposed multi-layer structure are positively considered by using the proposed circuit transformation procedures. As a result, the compact low ass filter (LPF) not only has at least 50% more compact thickness than other reported compact structures, but also provides ideal LPF response between 0.5GHz and 5GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.8 s.99
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• pp.803-809
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• 2005

This paper presents a novel method of mutual coupling suppression between antenna elements for performance improvement in planar array antenna system. Two miniature patch antenna elements satisfied IEEE 802.1 la($5.75\~5.35\;GHz,\;5.75\~5.85\;GHz$) are used for this research, they are arrayed by half wave length interval. It is observed about -20 dB mutual coupling between each antenna element at center frequency. To suppress mutual coupling, the arrayed antennas with a reversed 'U' structure are observed below -30 dB mutual coupling at IEEE 802.1la band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.3
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• pp.181-189
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• 2019

In this study, a triple-band antenna that can be used in WLAN(Wireless Local Area Network) at 2.4 GHz, 5.8 GHz, and 5G at 3.5 GHz is fabricated. The proposed antenna uses a parasitic element to show the triple band, and the reflector is used at a distance of ${\lambda}/4$ from the antenna to reduce the Specific Absorption Rate(SAR). Its dimensions are $100{\times}75{\times}1.6mm^3$ and each parameter value is optimized for better performance and a lower SAR value. As a result, we obtained a bandwidth of 540 MHz(2.02~2.56 GHz), 390 MHz(3.39~3.78 GHz), and 1,210 MHz(5.56~6.77 GHz) based on the reflection loss factor of -10 dB. In addition, the SAR values of the antenna with reflector are observed to reduce below the SAR value of international standard.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.428-434
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• 2009

In this paper, we propose an U-slot microstrip antenna with the U-shaped parasitic patches. U-slot and parasitic patches make two resonant frequencies and one additional resonant frequency, respectively, so that the impedance band-width of the antenna is expanded. The size of radiator part is $64{\times}53\;mm^2$ and the entire size of the antenna is $150{\times}150{\times}11.5\;mm^3$. The measured bandwidth is $1.85{\sim}2.40\;GHz$. Thus, our antenna can be used for DCS1900, WCDMA and WiMax services. The radiation characteristic is almost same in the bandwidth, the beam width is about $60^{\circ}$, and the gain is more than 7 dBi.

• Journal of IKEEE
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• v.22 no.1
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• pp.80-86
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• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.274-281
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• 2005

A new resonant pulse converter for energy harvesting is proposed. The converter transfers energy from a low-voltage AC current to a battery. The low-voltage AC current source is an equivalent of the piezoelectric generator, which converts the mechanical energy to the electric energy. The converter consists of a full-bridge rectifier having four N-type MOSFETs and a boost converter haying N-type MOSFET and P-type MOSFET instead of diode. Switching of MOSFETs utilizes the capability of the $3^{rd}$ regional operation. The operational principles and switching method for the power control of the converter are investigated with the consideration of effects of the parasitic capacitances of MOSFETs. Simulation and experiment are performed to prove the analysis of the converter operation and to show the possibility of the $\mu$W energy harvesting.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.285-285
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• 2011

최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력의 증가 등이 문제되고 있다. 대표적인 휘발성 메모리인 dynammic random access memory (DRAM)의 경우, 소자의 집적화가 진행됨에 따라 저장되는 정보의 양을 유지하기 위해 캐패시터영역의 복잡한 공정을 요구하게 된다. 하나의 캐패시터와 하나의 트랜지스터로 이루어진 기존의 DRAM과 달리, single transistor (1T) DRAM은 silicon-on-insulator (SOI) 기술을 기반으로 하여, 하나의 트랜지스터로 DRAM 동작을 구현한다. 이러한 구조적인 이점 이외에도, 우수한 전기적 절연 특성과 기생 정전용량 및 소비 전력의 감소 등의 장점을 가지고 있다. 또한 strained-Si 층을 적용한 strained-Silicon-On-Insulator (sSOI) 기술을 이용하여, 전기적 특성 및 메모리 특성의 향상을 기대 할 수 있다. 본 연구에서는 sSOI 기판위에 1T-DRAM을 구현하였으며, impact ionization과 gate induced-drain-leakage (GIDL) 전류에 의한 메모리 구동 방법을 통해 sSOI 1T-DRAM의 메모리 특성을 평가하였다. 그 결과 strain 효과에 의한 전기적 특성의 향상을 확인하였으며, GIDL 전류를 이용한 메모리 구동 방법을 사용했을 경우 낮은 소비 전력과 개선된 메모리 윈도우를 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.130-130
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• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.