• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.459-460
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• 2015

본 논문에서는 2개의 MOSFET으로 구성된 Half-bridge 회로를 구동할 때, 각 MOSFET의 기생성분을 고려하여 게이트 신호를 분석한다. 특히 MOSFET 구동시 게이트 전압에 따른 구간별 등가회로를 구성, 각 구간에서 다른 MOSFET에 상호적으로 미치는 영향을 수식적으로 분석하고, 시뮬레이션을 통해 스위칭 특성을 검증한다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.2 no.2
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• pp.30-37
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• 1991

The modified method which determines the extrinsic parameters at the small signal equivalent model for GaAs MESFET is presented. It is important that extrinsic parameters are completely eliminated, in order to calculate exact intrinsic parameters. Extrinsic circuit is established by transmission lines, parasitic inductors and capacitors. After these are extracted by S-parameters, intrinsic parameters are calculated. Especially, frequency dependence of parastic inductance and capacitance is considerally constant.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.165-168
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• 2002

Accurate circuit simulation models for embedded RF passive components in LTCC provide a way to efficiently design high performance RF modules. Particularly, consideration of unavoidable parasitic components is required certainly. In this study, the parasitic components which is appeared from 3-D structure is considered.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.21-22
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• 2015

플라이백 컨버터에서 발생하는 EMI 공통모드 잡음은, 스위치 turn-off에서 1차 측 누설 인덕턴스로 인한 기생 진동과 turn-on에서 발생하는 2차 측 출력회로의 기생 진동으로 구성된다. 차동모드 잡음은 직류전원의 스위칭 전류로 인한 전압 강하 성분으로 나타나며 직류전원 임피이던스에 비례하여 증가한다. 1차 측 기생진동은 느린 속도의 일반 다이오드와 직렬저항 삽입으로, 2차 측기생진동은 정류 다이오드의 RC 스너버로 감소 시킨다. 누설 인덕턴스가 큰 UU코어 EMI 필터가 잡음 감소에 유효함을 보인다.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.145-146
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• 2016

일반적인 boost PFC 컨버터는 한 개의 스위칭 소자를 사용하고 구조가 간단하지만 높은 도통손실과 스위칭 손실 때문에 낮은 효율을 갖는다. bridgeless boost PFC 컨버터는 일반적인 boost PFC 에 비해 낮은 손실을 갖는 이점이 있다. 또한 컨버터의 동작 모드 중 CRM 방식은 낮은 스위칭 손실을 갖는 이 점이 있다. 본 논문에서는 이러한 CRM 모드로 동작하는 bridgeless boost PFC 컨버터를 해석하는 경우 기존의 방법으로 해석하여 구현하면 주파수가 커지는 영역에서 오차가 커지게 된다. 따라서 본 논문에서는 반도체 스위치의 기생 커패시터를 추가하여 해석하는 것을 제안하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.362-370
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• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.176-177
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• 2008

이 논문에서는 $0.35{\mu}m$ 공정으로 제작된 MOSFET의 고주파 동작 특성을 분석하였다. Multi-finger 형태인 게이트 폭의 길이 변화에 따른 특성 변화를 BSIM3v3 모델과 외부 기생 파라미터를 포함한 lumped element를 이용해 모델링을 하였다. 또한 Multi-finger 게이트 구조에서 게이트 finger 수의 증가에 따라 생기는 특성 변화를 각각의 구조에 따라 추출된 주요 기생 파라미터의 변화를 통해 분석하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.485-490
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• 2010

We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1076-1085
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• 2001

In this paper, the FMM(Fast Multipole Method) combined with GMRES(Generalized Minimal RESidual Method) matrix solver is used to extract the parasitic impedance for complicated 3-D structures in uniform dielectric materials which limit the use of MoM(Method of Moment) due to its large computation time and memory requirement. This algorithm is a fast multipole-accelerated method based on quasistatic analysis and is very efficient for computing impedance between conductors. This paper proved the accuracy and efficiency of the FMM by comparing with MoM in simple examples. Finally the parasitic impedance of FC-PGA(Flip Chip Pin Grid Array) Package pins has been extracted by this algorithm and we have considered the possibility of the EMI/EMC problem caused by the signal interference.