• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.1
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• pp.50-58
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• 2003

Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.93-98
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• 2003

This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.

• Proceedings of the Korea Water Resources Association Conference
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• 1991.07a
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• pp.5-12
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• 1991

수자원 관련 연구 및 설계는 대부분 수문자료의 분석으로보터 출발하며, 따라서 수문자료의 효율적 관리 및 제공시스템의 필요성이 강조되어 왔다. 또한 설계회사 또는 학계, 연구소 등에서 수문자료의 분석시 퍼스날 컴퓨터를 이용하는 경우가 상당히 많으며, 단위 프로젝트에 필요한 비교적 적은 양 - 예를 들어 전국 중 특정 수계만을 대상으로 하는 경우 - 의 수문자료는 퍼스날 컴퓨터로도 처리가 가능하므로, 프로젝트 단위 수문자료의 검색, 출력 및 기본적 분석기능을 제공하는 퍼스날 컴퓨터용 수문데이타베이스의 개발 필요성이 제기되었다. PCHISS(Personal Computer Hydrological Information Support System)는 이러한 필요성에 의해 폭넓게 보급, 사용되고 있는 퍼스날 컴퓨터 - MS-DOS로 운영되는 IBM 호환 16비트 AT 또는 XT - 를 대상으로 상기한 수문자료의 검색, 출력 및 기본적 분석기능과 관측소 정보의 출력기능을 제공하도록 개발되었다. 개발에 사용된 언어는 C언어이며, C언어 프로그램에 의해 색인화된 자료처리기능을 제공하는 C-ISAM(C-Indexed Sequential Access Method)이라는 라이브러리를 사용하였다. 개발된 수문데이타베이스는 반복되는 수문자료의 검색, 출력 및 분석업무의 효율성 제고를 기할 수 있으며, 퍼스날 컴퓨터 및 보조기억장치를 포함한 주변장치의 성능이 계속 향상되고, 반면 가격은 상대적으로 낮추어지고 있으므로 프로젝트 단위의 수문자료관리시스템의 역할을 충분히 수행할 수 있을 것으로 기대된다.

• Annual Conference of KIPS
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• 2005.11a
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• pp.1375-1378
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• 2005

향후 국내에서 개발되는 저궤도 관측위성의 고성능 탑재컴퓨터로 유럽에서 자체적으로 개발하여 위성용으로 활용하고 있는 MCM-ERC32 를 사용할 예정이다. MCM-ERC32 는 크게 32-비트 ERC32SC 프로세서와 프로세서의 기능을 보완하고 추가적인 기능들을 제공하기 위해 제작된 ASIC인 VASI(Very Advanced Sparc Interface), 그리고 메모리(SRAM, DRAM, EEPROM, etc.)로 구성되어 있다. 위성의 탑재소프트웨어를 설계 및 개발하는데 있어서 가장 기본적으로 요구되는 기능이 타이머이다. 탑재소프트웨어는 타이머를 통하여 태스크들의 관리와 스케쥴링 등을 수행하게 된다. 위성과 같이 높은 정확도가 요구되는 실시간 임베디드 시스템에서는 타이머의 구현이 매우 중요하다. ERC32SC 프로세서 자체에서도 RTC, GPT(General Purpose Timer), WDT(Watchdog Timer)와 같은 기본적인 타이머 기능을 제공하지만 VASI 에서도 클락과 사이클이라는 개념을 이용한 RTC 를 제공한다. 어느 타이머를 사용하는가는 전적으로 개발자의 선택이다. ERC32SC 프로세서에서 제공하는 타이머는 상용의 임베디드 시스템에서 제공하는 기능과 동일하다. 본 논문에서는 위성탑재소프트웨어 개발에 필요한 RTC 를 설계하기 위한 MCM-ERC32 에서 제공하는 VASI RTC 의 구조와 기능에 대하여 소개하고자 한다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.3
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• pp.25-31
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• 2003

In this paper, proposed is a control system for a galvanometer which is widely used fer laser display, laser processing and marking systems. The galvanometer with mirror is modeled as a second-order dynamic system Based on frequency responses and time domain responses of the developed model, a conventional PID controller is designed And it is implemented using a DSP(TMS320C32) chip with precision A/D and D/A converters. Through frequency response and experimental results, it is convinced that the proposed control system works well in real environment. Furthermore it is very easy to be connected to any PC because of USB communication port, and the cost of the marking system can be lowered very much because the DSP do the all the jobs for generating font motion as well as controlling the galvanometer.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.259-264
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• 2014

IEEE 802.15.4 has been emerging as the popular choice for various monitoring and control applications. In this paper, a fault management system for DC power-lines has been designed using IEEE 802.15.4, in order to monitor DC power-lines in real time, and to rapidly detect faults and shut off the line where such faults occur. Numbers were allocated for each node and unslotted CSMA-CA method of IEEE 802.15.4 was used, the performance of which was analyzed by a simulation. For such purpose, a total of 60 bits of the control data consisting of 16 bits of the current, 16 bits of the amplitude, 28 bits of the terminal state data were sent out, and the packet transfer rate and the transmission delay time of the fault management system for DC power-lines were measured and analyzed. When the traffic load was 330 packets per second or lower, the average delay time was shown to be shorter than 0.02 seconds, and when the traffic load was 260 packets per second or lower, the packet transfer rate was shown to be 99.99% or higher. Therefore, it was confirmed that the stringent condition of US Department of Energy (DOE) could be satisfied if the traffic load was 260 packets per second or lower, The results of this study can be utilized as basic data for the establishment of the fault management system for DC power-lines using IEEE 802.15.4.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.369-377
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• 2008

Today, Ethernet technology is rapidly developing to have a bandwidth of 10Gbps beyond 1Gbps. In such high-speed networks, the existing method that host CPU processes TCP/IP in the operating system causes numerous overheads. As a result of the overheads, user applications cannot get the enough computing power from the host CPU. To solve this problem, the TCP/IP Offload Engine(TOE) technology was emerged. TOE is a specialized NIC which processes the TCP/IP instead of the host CPU. In this paper, we implemented a high-performance, lightweight TCP/IP(HL-TCP) for the TOE and applied it to an embedded system. The HL-TCP supports existing fundamental TCP/IP functions; flow control, congestion control, retransmission, delayed ACK, processing out-of-order packets. And it was implemented to utilize Ethernet MAC's hardware features such as TCP segmentation offload(TSO), checksum offload(CSO) and interrupt coalescing. Also we eliminated the copy overhead from the host memory to the NIC memory when sending data and we implemented an efficient DMA mechanism for the TCP retransmission. The TOE using the HL-TCP has the CPU utilization of less than 6% and the bandwidth of 453Mbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.657-666
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• 2002

In this paper, a new broadband phase shifter to adjust the slope of dispersive phase characteristic for frequency of transmission network was proposed. The new fundamental network consists of a fixed main line with a length of λ/2 at the center frequency and two double stubs, each with a length of λ/8 at the center frequency, which are open and shorted, respectively, and which are shunted at the edge points of the main line. Characteristic impedances of the main line and two parallel double stubs are adjusted to produce a minimum phase error and to obtain an input and output match at the desired phase shift. Especially, the proposed structure is especially suitable for a broadband phase shifter with large phase shifts more than 90$^{\circ}$, and it is operated in the octave bandwidth. To verify the usefulness of a new broadband phase shifter, each 45$^{\circ}$-, 90$^{\circ}$-, 180$^{\circ}$-bit phase shifter and 3-bit phase shifter(45$^{\circ}$-phase step), which is cascaded in series, operated at the center frequency 3 GHz were designed, fabricated and experimented. The measured results were in very close agreement with the corresponding simulation results over the bandwidth of I/O impedance match and phase error for each phase shift.