Design and Analysis of a $AB^2$ Systolic Arrays for Division/Inversion in$GF(2^m)$

$GF(2^m)$상에서 나눗셈/역원 연산을 위한 $AB^2$ 시스톨릭 어레이 설계 및 분석

  • 김남연 (경북대학교 컴퓨터공학과) ;
  • 고대곤 (대구교육대학교 전산교육과) ;
  • 유기영 (경북대학교 컴퓨터공학과)
  • Published : 2003.02.01

Abstract

Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

$GF(2^m)$상의 공개키 암호 시스템에서 $AB^2$ 연산은 효율적이고 기본적인 연산으로 잘 알려져 있다. 나눗셈/역원은 기본이 되는 연산으로, 내부적으로 $AB^2$ 연산을 반복적으로 수행함으로써 계산이 된다. 본 논문에서는 $GF(2^m)$상에서$AB^2$ 연산을 수행하는데 필요한 새로운 알고리즘과 그에 따른 병렬 입/출력 및 시리얼 입/출력 구조를 제안한다. 제안된 알고리즘은 최상위 비트 우선 구조를 기반으로 하고, 구조는 기존의 구조에 비해 낮은 하드웨어 복잡도와 적은 지연을 가진다 이는 역원과 나눗셈 연산을 위한 기본 구조로 사용될 수 있으며 암호 프로세서 칩 디자인의 기본 구조로 이용될 수 있고, 또한 단순성, 규칙성과 병렬성으로 인해 VLSI 구현에 적합하다.

Keywords

References

  1. W.W.Peterson and E.J.Weldon, Error correcting codes, MIT Press, MA, 1972
  2. D.E.R.Denning, Cryptography and data security, Addison-Wesley, MA, 1983
  3. A.Menezes, Elliptic Curve Public Key Cryptosystems, Kluwer Academic Publishers, Boston, 1993
  4. T.ElGamal, A public key cryptosystem and a signature scheme based on discrete logarithms, IEEE Trans. on Info. Theory, vol. 31(4), pp. 469-472, July 1985 https://doi.org/10.1109/TIT.1985.1057074
  5. I.S.Reed and T.K. Truong, The use of finite fields to computer convolutions, IEEE Trans. Inform. Theory, 21, pp.208-213, 1975 https://doi.org/10.1109/TIT.1975.1055352
  6. S.W.Wei, VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2m), Proc. IEEE Trans. Circuits and Systems, 44, pp.847-855, 1997 https://doi.org/10.1109/82.633444
  7. S.W.Wei, A Systolic Power Sum Circuit for GF(2m), IEEE Trans. Computers, 43, pp.226-229, 1994 https://doi.org/10.1109/12.262128
  8. C.L.Wang and J.H.Guo, New systolic arrays for C+AB2. inversion, and division in GF(2m), IEEE Trans. Computers, 49, pp.1120-1125, 2000 https://doi.org/10.1109/12.888047
  9. J.V.McCanny, R.A.Evans and J.G.Mcwhirter, Use of unidirectional data flow in bit-level systolic array chips, Electron.Lett., 22, pp. 540-541, 1986 https://doi.org/10.1049/el:19860368
  10. Nam-Yeun Kim and Kee-Young Yoo, 'A Power Sum Systolic Architecture in $GF(2^m)$,' Lecture Notes in Computer Science VOL 2344 Information Networkihg. Wiress Communications Technologies and Network Applications (LNCS 2344), pp. 409-417, Feb. 2002
  11. S.Y.Kung, VLSI Array Processors, Prentice-Hall, 1987
  12. K.Y.Yoo, A Systolic Array Design Methodology for Sequential Loop Algorithms, Ph.D. thesis, Rensselaer Polytechnic Institute, New York, 1992
  13. C.S.Yeh, I.S.Reed and T.K.Truong, Systolic multipliers for finite fields GF(2m), IEEE Trans. Comput.,vol.C-33, pp.357-360, Apr. 1984 https://doi.org/10.1109/TC.1984.1676441
  14. C.H.Liu, N.F.Huang, and C.Y.Lee, 'Computation of $AB^2$ Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture,' IEICE trans. fundamentals, Vol. E83-A, No. 12, December 2000
  15. 이형목, 김현성, 전준철, 유기영, 'GF(2m)상에서 $AB^2$연산을 위한 세미시스톨릭 구조,' 정보보호학회 논문지 제 12권 제 2호, 2002년 4월
  16. H.S.Kim, 'Bit-Serial AOP Arithmetic Architecture for Modular Exponentiation,' Ph.D.thesis, Kyungpook National University, 2001
  17. Daniel D. Gajski, Principles of Digital Design, Prentice-hall international. INC.,1997