• Journal of the Computational Structural Engineering Institute of Korea
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• v.30 no.6
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• pp.507-514
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• 2017

As BIM has been widely used in the field of architecture, efforts to apply BIM to civil engineering structures are increasing rapidly. Since commercial BIM softwares are focused on building structure, it is difficult to apply to alignment-based civil infrastructures. In this study, we proposed a method to generate an information model that reflects cant by sharing information between alignment-centered modeling tools and BIM authoring tools to manage information of railway track. The railway track modeling process consists of classifying structures into continuous and non-continuous structures, creating continuous structures by alignment-centered modeling tools, and using the shared alignment information to generate information model of the non-continuous structures. Non-continuous structures were generated by an algorithm that calculates the position and rotation information of each structure based on discretized railway alignment and cant information transmitted to the BIM authoring tools. The availabilities of proposed method were studied by applying to the osong test-line. Using the test model, it was shown that the objects were identified, the properties were extracted, and the quantities of each structure were calculated.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Journal of the Korea Society of Computer and Information
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• v.18 no.6
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• pp.63-70
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• 2013

In accordance with the advancement of IT, application systems with various and complex functions are being required. Such application systems are typically built based on database in order to manage data efficiently. But most object-oriented analysis design methodologies for developing web application systems have not been providing interconnections with the database. Since the requirements regarding the security issues increased, the importance of security has become emphasized. However, since the security is usually considered at the last step of development, it is difficult to apply the security during the whole process of system development, from the requirement analysis to implementation. Therefore, this paper suggests an object-oriented analysis and design methodology for secure database design from the requirement analysis to implementation. This object-oriented analysis and design methodology for secure database design offers correlations with database that most existing object-oriented analysis and design methodologies could not provide. It also uses UMLsec, the modeling language, to apply security into database design. In addition, in order to implement security, RBAC (Role Based Access Control) of relational database is used.

• Journal of the Earthquake Engineering Society of Korea
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• v.15 no.3
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• pp.37-43
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• 2011

Reliability of piping systems is essential to the safety of any important industrial facilities. During an earthquake, damage to the piping system can occur. It can also cause considerable economic losses and the loss of life following earthquakes. Traditionally, the study of the secondary system was less important than primary structure system, however it has recently been emerging as a key issue for the effective maintenance of the structural system and to help reduce nonstructural earthquake damage. The primary objectives of this study are to evaluate seismic design requirements and the seismic performance of gas and fire protection piping systems installed in reinforced concrete (RC) buildings. In order to characterize the seismic behavior of the existing piping system in an official building, 10 simulated earthquakes and 9 recorded real earthquakes were applied to ground level and the building system by the newmark average acceleration time history method. The results developed by this research can be used for the improvement of new seismic code/regulatory guidelines of secondary systems as well as the improvement of seismic retrofitting or the strengthening of the current piping system.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.4
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• pp.563-568
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• 2007

This paper presents a methodology for predicting nonlinear time series based on the neural network with weighted fuzzy membership functions (NEWFM). The degree of classification intensity is obtained by bounded sum of weighted fuzzy membership functions extracted by NEWFM, then weighted average defuzzification is used for predicting nonlinear time series. The experimental results demonstrate that NEWFM has the classification capability of 92.22% against the target class of GDP. The time series created by NEWFM model has a relatively close approximation to the GDP which is a typical business cycle indicator, and has been proved to be a useful indicator which has the turning point forecasting capability of average 12 months in the peak point and average 6 months in the trough point during 5th to 8th cyclical period. In addition, NEWFM measures the efficiency of the economic indexes by the feature selection and enables the users to forecast with reduced numbers of 7 among 10 leading indexes while improving the classification rate from 90% to 92.22%.

• Journal of Biomedical Engineering Research
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• v.25 no.6
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• pp.565-573
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• 2004

In this paper, we proposed a heart activity control model for simulation of the aortic sinus baroreceptor, which was the most representative baroreceptor sensing the variance of pressure in the cardiovascular system. And then, the heart activity control model composed electric circuit model of the cardiovascular system with baroreflex control and time delay sub-model to observe the effect of time delay in heart period and stroke volume under the regulation of baroreflex in the aortic sinus. The mechanism of time delay in the heart activity baroreflex control model is as follows. A control function is conduct sensing pressure information in the aortic sinus baroreceptor to transmit the efferent nerve through central nervous system. As simulation results of the proposed model, we observed three patterns of the cardiovascular system variability by the time delay. First of all, if the time delay over 2.5 second, aortic pressure and stroke volume and heart rate was observed non-periodically and irregularly. However, if the time delay from 0.1 second to 0.25 second, the regular oscillation was observed. And then, if time delay under 0.1 second, then heart rate and aortic pressure-heart rate trajectory were maintained in stable state.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• KIPS Transactions on Software and Data Engineering
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• v.5 no.2
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• pp.69-78
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• 2016

Ischemic stroke is a disease that the brain tissues cannot function by reducing blood flow due to thrombosis or embolisms. Due to the nature of the disease, it is most important to identify the status of cerebral vessel and the medical images are necessarily used for its diagnosis. Among many indicators, brain MRI is most widely utilized because experts can effectively obtain the semantic information such as cerebral anatomy aiding the diagnosis with it. However, in case of emergency diseases like ischemic stroke, even though a intelligent system is required for supporting the prompt diagnosis and treatment, the current systems have some difficulties to provide the information of medical images intuitively. In other words, as the current systems have managed the medical images based on the basic meta-data such as image name, ID and so on, they cannot consider semantic information inherent in medical images. Therefore, in this paper, to provide core information like cerebral anatomy contained in brain MRI, we suggest a template-driven medical images mapping method. The key idea of the method is defining the mapping characteristics between anatomic feature and representative images by using template images that can be representative of the whole brain MRI image set and revealing the semantic relations that only medical experts can check between images. With our method, it will be possible to manage the medical images based on semantic.

• Korean Journal of Clinical Laboratory Science
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• v.51 no.4
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• pp.397-405
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• 2019

Quantitative electroencephalography (QEEG) has been widely used in research and clinical fields. QEEG has been widely used to objectively document cerebral changes for the purpose of identifying the electrophysiological biomarkers across various clinical symptoms and for the stimulation of specific cortical regions associated with cognitive function. In electroencephalography (EEG), the difference in quantitative and qualitative analyses is discriminated not by its measurement methods and relevant clinical or research environments, but by its analysis methods. When performing a qualitative analysis, it is possible for a medical technologist or experienced researchers to read the EEG waveforms to exclude artifacts. However, the quantitative analysis is still based on mathematical modeling, and all EEG data are included for the analysis, leading the results to be affected by unexpected artifacts. In the hospital setting, the case that the medical technologists in charge of the EEG test perform academic research has been little reported, compared to other clinical physiological measurement-based research. This is because there are few laboratories specialized in clinical physiological research. In this respect, this study is expected to be utilized as a basic reference material for medical technologists, students, and academic researchers, all of whom would like to conduct a quantitative analysis.