• 제목/요약/키워드: 그래프신호처리

검색결과 47건 처리시간 0.023초

Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis (신호전이그래프에 기반한 비동기식 논리합성의 고유한 특성을 고려한 신호전이그래프의 자동생성)

  • Kim, Eui-Seok;Lee, Jeong-Gun;Lee, Dong-Ik
    • The KIPS Transactions:PartA
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    • 제9A권3호
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    • pp.351-362
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    • 2002
  • Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

Synthesis of Asynchronous Circuits from Free-Choice Signal Transition Graphs with Timing Constraints (시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로의 합성)

  • Jeong, Seong-Tae;Jeong, Seok-Tae
    • The KIPS Transactions:PartA
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    • 제9A권1호
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    • pp.61-74
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    • 2002
  • This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

Low-complexity Sampling Set Selection for Bandlimited Graph Signals (대역폭 제한 그래프신호를 위한 저 복잡도 샘플링 집합 선택 알고리즘)

  • Kim, Yoon Hak
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제24권12호
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    • pp.1682-1687
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    • 2020
  • We study the problem of sampling a subset of nodes of graphs for bandlimited graph signals such that the signal values on the sampled nodes provide the most information in order to reconstruct the original graph signal. Instead of directly minimizing the reconstruction error, we focus on minimizing the upper bound of the reconstruction error to reduce the complexity of the selection process. We further simplify the upper bound by applying useful approximations to propose a low-weight greedy selection process that is iteratively conducted to find a suboptimal sampling set. Through the extensive experiments for various graphs, we inspect the performance of the proposed algorithm by comparing with different sampling set selection methods and show that the proposed technique runs fast while preserving a competitive reconstruction performance, yielding a practical solution to real-time applications.

Sampling Set Selection Algorithm for Weighted Graph Signals (가중치를 갖는 그래프신호를 위한 샘플링 집합 선택 알고리즘)

  • Kim, Yoon Hak
    • The Journal of the Korea institute of electronic communication sciences
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    • 제17권1호
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    • pp.153-160
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    • 2022
  • A greedy algorithm is proposed to select a subset of nodes of a graph for bandlimited graph signals in which each signal value is generated with its weight. Since graph signals are weighted, we seek to minimize the weighted reconstruction error which is formulated by using the QR factorization and derive an analytic result to find iteratively the node minimizing the weighted reconstruction error, leading to a simplified iterative selection process. Experiments show that the proposed method achieves a significant performance gain for graph signals with weights on various graphs as compared with the previous novel selection techniques.

매크로-스타 그래프에서의 일-대-다 방송 알고리즘

  • 이형옥;류광택
    • Proceedings of the Korean Information Science Society Conference
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    • 한국정보과학회 2000년도 봄 학술발표논문집 Vol.27 No.1 (A)
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    • pp.597-599
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    • 2000
  • 대규모 병렬 컴퓨터에서 메시지를 가진 한 노드에서 다른 모든 노드들로 그 메시지를 전달하는 방송은 데이터의 복제, 신호 처리와 같은 다양한 응용프로그램에서 이용되는 중요한 통신 패턴이다. 매크로-스타 그래프는 스타 그래프를 기본 모듈로 가지면서 스타 그래프가 갖는 노드 대칭성, 최대 고장 허용도, 계층적 분할 성질을 갖고, 스타 그래프보다 망 비용이 개선된 상호 연결망으로 최근에 제안되었다. 본 논문에서는 매크로-스타 그래프의 계층적 분할 성질과 기본 모듈을 이용한 매크로-스타 그래프에서의 일-대-다 방송알고리즘을 제안한다.

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Efficient Sampling of Graph Signals with Reduced Complexity (저 복잡도를 갖는 효율적인 그래프 신호의 샘플링 알고리즘)

  • Kim, Yoon Hak
    • The Journal of the Korea institute of electronic communication sciences
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    • 제17권2호
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    • pp.367-374
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    • 2022
  • A sampling set selection algorithm is proposed to reconstruct original graph signals from the sampled signals generated on the nodes in the sampling set. Instead of directly minimizing the reconstruction error, we focus on minimizing the upper bound on the reconstruction error to reduce the algorithm complexity. The metric is manipulated by using QR factorization to produce the upper triangular matrix and the analytic result is presented to enable a greedy selection of the next nodes at iterations by using the diagonal entries of the upper triangular matrix, leading to an efficient sampling process with reduced complexity. We run experiments for various graphs to demonstrate a competitive reconstruction performance of the proposed algorithm while offering the execution time about 3.5 times faster than one of the previous selection methods.

Fast Sampling Set Selection Algorithm for Arbitrary Graph Signals (임의의 그래프신호를 위한 고속 샘플링 집합 선택 알고리즘)

  • Kim, Yoon-Hak
    • The Journal of the Korea institute of electronic communication sciences
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    • 제15권6호
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    • pp.1023-1030
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    • 2020
  • We address the sampling set selection problem for arbitrary graph signals such that the original graph signal is reconstructed from the signal values on the nodes in the sampling set. We introduce a variation difference as a new indirect metric that measures the error of signal variations caused by sampling process without resorting to the eigen-decomposition which requires a huge computational cost. Instead of directly minimizing the reconstruction error, we propose a simple and fast greedy selection algorithm that minimizes the variation differences at each iteration and justify the proposed reasoning by showing that the principle used in the proposed process is similar to that in the previous novel technique. We run experiments to show that the proposed method yields a competitive reconstruction performance with a substantially reduced complexity for various graphs as compared with the previous selection methods.

Fairness Analysis on Real-World Graph Data (실세계 그래프 데이터에 대한 공정성 분석)

  • Hojung Shin;Yeon-Chang Lee;Sang-Wook Kim
    • Proceedings of the Korea Information Processing Society Conference
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    • 한국정보처리학회 2024년도 춘계학술발표대회
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    • pp.678-679
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    • 2024
  • 그래프 신경망(Graph Neural Network, GNN)은 실세계 그래프 데이터에 대한 다양한 다운스트림 작업들에서 우수한 성능을 보여 왔다. 그러나, 최근 연구는 GNN 의 예측 결과가 데이터 내 특정 집단에 대한 차별을 내포할 수 있음을 지적했다. 이러한 문제를 해결하기 위해, 공정성을 고려할 수 있는 GNN 방법들이 설계되어 오고 있으나, 아직 실세계 그래프 데이터가 공정성 관점에서 어떠한 특성을 가지고 있는지에 대한 분석은 충분히 이루어지지 않았다. 따라서, 본 논문에서는 다양한 공정성 평가 지표를 활용하여 실세계 그래프 데이터의 공정성을 비교 분석한다. 실험 결과, 실세계 그래프 데이터들은 도메인 혹은 평가 지표에 따라 다른 특성을 가진다는 것을 확인하였다.

Specification and Synthesis of Speed-independent Circuit using VHDL (VHDL을 이용한 속도 독립 회로의 기술과 합성)

  • Jeong, Seong-Tae
    • The Transactions of the Korea Information Processing Society
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    • 제6권7호
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    • pp.1919-1928
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    • 1999
  • There are no standard language for the specification of speed-independent circuits because existing specification methods are designed appropriately to each synthesis methodology. This paper suggests a method of using VHDL, a standard hardware description language, for the specification and synthesis of speed-independent circuits. Because VHDL is a multi-purpose language, we define a subset of VHDL which can be used for the synthesis. We transform the VHDL description into a signal transition graph and then synthesize speed-independent circuits by using a previous synthesis algorithm which uses a signal transition graph as the specification method. We suggest a systematic transformation method which transforms each VHDL statement into a partial signal transition graph and then merges them into a signal transition graph. This work is a step towards to the development of an integrated framework in which we can utilizes the existing CAD tools based on VHDL. Also, this work will enable a easier migration of the current circuit designers into asynchronous circuit design.

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A Study on the Formal Specification of Civil Defense Alarm (민방위 경보음의 정형 명세에 관한 연구)

  • Oh, Hye-Yoon;Jung, Sun-il;Kwon, Gihwon
    • Proceedings of the Korea Information Processing Society Conference
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    • 한국정보처리학회 2015년도 추계학술발표대회
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    • pp.1078-1079
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    • 2015
  • 본 논문에서는 신호 시제 논리 명세를 통하여 민방위 경보음을 정형적으로 명세한다. 논리를 기반으로 한 정형 명세는 비정형 명세에 비하여 분명하고, 간결하며, 기계처리가 가능한 이점을 제공한다. 민방위 경보음에 대한 시간의 흐름에 따른 주파수의 변화를 그래프로 그린 후에 이를 신호시제 논리로 명세하고자 한다.