• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.469-470
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• 2010

• Proceedings of the Korean Environmental Sciences Society Conference
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• 2019.10a
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• pp.133-133
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• 2019

• Proceedings of the Korean Ceranic Society Conference
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• 2004.04b
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• pp.48.3-48.3
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• 2004

• Proceedings of the Korean Nuclear Society Conference
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• 2002.10a
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• pp.305.1-305
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• 2002

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.81-87
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• 2001

In a dynamically changing environment, the manager of a maintenance and remodeling (M/R) program is confronted with an increasing complexity of coordinating and cooperating multi-resource constrained multiple projects. The root causes of the complexity, uncertainty and interdependence, cause an internal disruption of an activity and chain reactions of disturbance propagation that deteriorate the stability and manageability of the program. This paper evaluates previous endeavors to apply production control and management techniques to the construction industry, and investigates the possibility of applying other management concepts and theories to organizational program management. In particular, this paper proposes a buffer allocation model by which periodic buffers are allocated in the flows of program constraint resources to stabilize a program master schedule instead of protecting individual activities. Comparative experiments by Monte Carlo simulations illustrate improved performance of the proposed model in terms of program's goals: productivity, flexibility, and long-term stability.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1838-1855
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• 2008

The manufacturing industry seeks for improvements in efficiency at the manufacturing process. This paper presents a method for effective real time dispatching for parallel machines with multi product that minimizes mean tardiness and maximizes the quality of the product. What is shown in this paper is that using the Rolling Horizon Tabu search method in the real time dispatching process, mean tardiness can be reduced to the minimum. The effectiveness of the method presented in this paper has been examined in the simulation and compared with other dispatching methods. In fact, using this method manufacturing companies can increase profits and improve customer satisfaction as well.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.11-11
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• 2001

본 논문에서는 카운터와 커패시터를 사용하여 시간 정보로부터 디지털 출력 값을 얻을 수 있는 새로운 시간-디지털 변환기를 제안하였다. 기존의 시간-디지털 변환회로의 경우 디지털 출력 값을 얻기 위해서는 입력 신호가 인가된 후 입력 시간보다 더 긴 공정시간이 필요하였다. 또한 입력 신호의 시간 간격에 무관하게 카운터의 클럭 주파수가 일정하여 변환된 디지털 값의 분해도는 항상 일정하였다. 그러나 본 논문에서 제안한 시간-디지털 변환 회로는 입력 신호가 인가됨과 동시에 지연시간 없이 디지털 출력 신호를 얻을 수 있으며, 또한 수동소자의 값을 변화시킴으로서 원하는 입력 시간 영역과 분해도를 쉽게 구현할 수 있다.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.06a
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• pp.219-222
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• 2001

본 연구의 내용은 실시간 서비스 트래픽, 즉 보장형 서비스를 위한 스케줄링 알고리즘들에 대한 성능분석에 대한 연구이다. 특히 실시간 데이터 전송의 경우, 작은 지연 시간을 요구하면서 안정된 QoS를 요구하고 있다. 기존에 알려진 FQ, WFQ, WF2Q, Virtual Clock 스케줄링 알고리즘들을 사용해서 대기 큐의 수학적 모델이 아닌 시뮬레이션 도구를 사용해서, 지연에 민감한 보장형 서비스 트래픽에 대한 시간 복잡도, 공정성, 처리율 측면으로 성능을 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.35-43
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• 2006

In the paper, we propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in Statistical Static Timing Analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of proposed method has been verified on ISCAS85 benchmark circuits with $0.16{\mu}m$ model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.