• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.39-46
• /
• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.7
• /
• pp.29-35
• /
• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.87-93
• /
• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• The Journal of Information Technology
• /
• v.6 no.4
• /
• pp.11-23
• /
• 2003

We proposes that Design of the Digital Neuron Processor and Development of the Algorithm for the real time object recognition in the making Automatic system which uses the residue number system making the high speed operation possible without carry propagation, in this paper. Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed. The Designed circuits are descripted by C language and VHDL and synthesized by Compass tools. Finally, the designed processor is fabricated in 0.8${\mu}m$ CMOS process. Result of simulations shows that critical path delay time is about 19nsec and operation speed is 0.6nsec and the size can be reduced to 1/2 times co pared to the neural networks implemented by the real number operation unit. The proposed design the digital neuron processor can be implemented of the object recognition in the making Automatic system with desired real time processing.

• Korean Journal of Construction Engineering and Management
• /
• v.3 no.1 s.9
• /
• pp.91-96
• /
• 2002

The purpose of this study is to present a systemized flow of temporary facility(TF) planning information. The current TF planning tends to be established by subjective decision making of field workers. Therefore TF planning needs more systemized information flow to provide a reliable schedule. The study was implemented through interview with experts for reliable TF planning. The main contents of the study are as follows; 1) TF planning process model(IDEF0) are established. 2) Various information flow diagrams proposed to support TF planning decision-making. The study recommends that, as a future research, the computer system be developed for application of the information flow.

• Proceedings of the Korean Institute Of Construction Engineering and Management
• /
• 2006.11a
• /
• pp.523-528
• /
• 2006

The management of construction materials is one of the important administration factor to perform construction projects. If it is not flexible to supply necessary materials to a workplace at a proper time, some problems such as a construction cost increase, an operation delay, a lowering of work efficiency and etc. could occur during the progress of work. Therefore, tracking the precise location of materials is important and necessary to input materials in the accurate place. Although Location sensing techniques comprise GPS, Active Badge, EasyLing and so forth, there are technical limitations to apply these techniques on construction site. Accordingly, in this paper, we propose the technically feasible method to automatically locate materials on site using recent RFID and wireless network technologies.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.838-844
• /
• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.2
• /
• pp.378-385
• /
• 2016

The internal circuit of the bus-bar for an electrical switch board is a prime cause of electric shock and short circuit accidents due to the exposure of live parts. Electrical fires can also be caused by animals and foreign substances in the switchboard that connect the components with a difficult structure resulting in overheating due to an increase in contact resistance. Preventing these types of accidents is a prime concern in the manufacturing process, such as cutting and bending. In this study, the cutting bus bar of a switch board contained improved modules as a flame retardant that isolates a separate blocks to prevent such problems. This was implemented as a scalable and flexible means of reducing electrical switchboard hazards to offer a safe switch board bus-bar structure of a new connecter type

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.1
• /
• pp.119-124
• /
• 2010

The MAC layer in ad-hoc network which makes network of nodes without infrastructure for a time has became an issue to reduce delay, allocate fairly bandwidth, control TX/RX power and improve throughput. Specially, the problem to reduce power consumption in ad-hoc network is very important part as ad-hoc devices use the limited battery. For solution of the problem, many power control algorithms, such as distribute power control, PCM (Power Control MAC) and F-PCF (Fragmentation based PCM), are proposed to limit power consumption until now. Although the algorithms are designed to minimize power consumption, the latency communication zone is generated by power control of RX/TX nodes. However the algorithms don't suitably reuse the space. In this paper proposes the algorithm to improve data throughput through Spatial Reuse based on a power control method.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.1
• /
• pp.242-249
• /
• 2010

As the scale of domestic building construction becomes larger, more complicated and more specialized, demands for quality improvement, cost reduction and construction period shortening increase. Construction materials management becomes a main factor to perform the project successfully. Therefore, various researches using RFID(Radio Frequency Identification) are being studied to manage the construction materials efficiently. This research aims to suggest the method of construction materials management using RFID in apartment housing. First, the technical properties of RFID are grasped. Second, problems are extracted by analyzing the case studies and related research using RFID in construction field. Third, construction materials are classified according to the construction process and process of materials management is analyzed. Lastly, method of construction materials management using RFID is suggested. The results of this research are expected to contribute the improvement of construction productivity through effective material management.