• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1390-1403
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• 1998

Database sharing system (DSS) refers to a system for high performance transaction processing. In DSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory, a separate copy of operating system, and a DB'\fS. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. However, since multiple nodes may be simultaneously cached a page, cache consistency must be cnsured so that every node can always access the'latest version of pages. In this paper, we propose efficient cache consistency schemes in DSS, where the database is logically partitioned using primary copy authority to reduce locking overhead, The proposed schemes can improve performance by reducing the disk access overhead and the message overhead due to maintaining cache consistency, Furthermore, they can show good performance when database workloads are varied dynamically.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.11
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• pp.810-819
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• 2006

This paper proposes an Adaptive Double Buffer Model. As a new FIFO buffer model, this technique minimizes packet losses from network congestion by logically managing buffers. It allocates the spare spaces of non-congested buffers to congested buffers by allowing receive/send buffers to share two queues, and hence it minimizes packet losses. In contrast to the buffer model utilizing a free list, this buffer model can prevent the bubble phenomenon caused by a memory leak and thereby apply to a network buffer in a restricted environment. Also, compared with the model using an way, this model brings maximum 100 percent improvement in accepting packets and compared with the model utilizing a free list, this model has the similar efficiency Results of the performance test on Adaptive Double Buffer Model, shows that this proposed model decreases packet losses and enhances memory efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.80-90
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• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.1
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• pp.49-56
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• 2004

Load imbalance is a serious impediment to achieving good performance in parallel processing. Global load balancing schemes cannot adequately manage to balance parallel tasks generated from a single application. Dynamic loop scheduling methods are known to be useful in balancing parallel loops on shared-memory multiprocessor machines. However, their centralized nature causes a bottleneck for the relatively small number of processors in a network of workstations because of order-of-magniture differences in communication overheads. Moreover, improvements of basis loops scheduling methods have not effectively dealt with irregularly distributed workloads in parallel loops, which commonly occur in applications for a network of workstation. In this paper, we present a new reconfigurable and decentralized balancing method for parallel loops on a network of workstations. Since our method supplements performance balancing with those tranditional load balancing methods, it minimizes the overall execution time.

• The Journal of Korean Association of Computer Education
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• v.15 no.3
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• pp.37-47
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• 2012

One of the major goals in high school Informatics is for students to develop creative problem-solving abilities based on knowledge on computer science. Thus, the contents of the textbooks should be accurate and appropriate. However, we discovered that the current Informatics textbooks contain the untrue and/or inappropriate descriptions of main memory and virtual memory. The textbooks describe that main memory is composed of RAM and ROM. The virtual memory is described as a technique in which a part of the secondary storage is utilized as main memory to execute an application of which size is larger than that of main memory. In this study, we attempted to uncover the root causes of the fallacies, and suggest the accurate explanations by comparing with renowned books adopted in most schools worldwide including USA. Our study reveals that it is inappropriate to include ROM in main memory from the memory hierarchy perspective. Virtual memory is a technique that provides convenience to programmers, through which an operating system loads the necessary portion of a program from secondary storage to main memory. As for the advantages of virtual memory in the current computer systems, the focus should be on providing the effective multitasking capability, rather than on executing a larger program than the size of main memory. We suggest that it is appropriate to exclude virtual memory in textbooks considering its complexity.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06d
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• pp.141-144
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• 2007

이동 애드 혹 네트워크(MANET)는 지리적, 환경적인 요인으로 기존의 네트워크를 설치할 수 없는 산악과 같은 고립된 지역에 설치할 수 있는 이동 노드들로 구성된 네트워크이다. 또한 인포스테이션은 전송지연에 민감하지 않는 정보들을 적은 비용으로 효율적으로 전송할 수 있는 시스템이다. 본 논문에서는 등산객이 무선 이동 노드를 휴대함으로서 이동 애드 혹 네트워크를 구성하고, 또한 인포스테이션이 결합된 등산객 조난 구조 시스템을 제안한다. 등산객은 이동 중에 만나는 다른 등산객과 위치정보를 공유하고, 이를 인포스테이션에 전송함으로써 다른 노드들의 위치 추적을 가능하게 한다. 이 시스템은 노드들간의 연결이 지속적이지 않은, 노드의 이동성을 통한 간헐적인 네트워크를 구성하게 된다. 따라서 시스템 구축비용이 적게 들고, 또한 인포스테이션을 통해 노드에 저장되어 있는 위치정보를 전송함으로서 필요한 메모리 용량을 감소시키는 효과도 있다. 그러므로 제안된 시스템을 활용한다면, 조난된 등산객의 위치를 신속히 파악할 수 있어, 효율적인 구조 활동이 가능하게 할 것이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.827-829
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• 2009

현재 멀티 코어 프로세서는 많은 서버에 적용되어 사용되고 있으며, 향후에는 하나의 프로세서 패키지에 포함될 코어의 개수는 계속해서 증가할 것이다. 그러나 현재 운영체제들은 멀티 코어 시스템을 멀티 프로세서 환경과 거의 동일하게 다루고 있으며 아직 멀티 코어 특성을 고려한 성능 최적화 시도는 미흡한 상태이다. 본 논문은 SMP와 NUMA 구조의 멀티 코어 프로세서 환경에서 통신 프로세스와 네트워크 인터럽트의 프로세서 친화도를 변화시키며 네트워크 처리율과 코어의 유휴 자원 양을 정량적으로 분석한다. 측정 결과 프로세서 친화도에 따라 통신 처리율은 크게 변하지 않지만 프로세서 자원의 요구량에는 크게 영향을 주는 것을 보인다. 또한 이러한 프로세서 자원의 영향은 멀티 코어 프로세서의 캐쉬 공유 구조 및 메모리 분산 구조와 밀접한 관계를 갖고 있음을 밝힌다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.348-351
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• 2009

유비쿼터스 사회를 실현하는 핵심기술인 u-GIS 공간정보 기술은 데이터 스트림 처리 시스템(Data Stream Management System)과 지리정보 시스템(Geography Information System)이 결합된 플랫폼인 u-GIS DSMS를 요구한다. u-GIS DSMS는 GeoSeonsor에서 수집되는 센서 테이터와 GIS의 공간정보 데이터를 결합하여 처리하는 공간영역질의가 다수 요구된다. 이런 공간영역질의들은 특정 지역에 밀집하게 등록되는 경향이 있으며, 유사한 프리디킷을 가질 가능성이 높다. 이러한 특징은 공간영역질의가 특정 지역에 밀집되면 다수의 비슷한 연산들이 반복적으로 처리하기 때문에 시스템 성능이 저하 될 것이다. 이를 해결하기 위해 영역질의 색인기법 연구가 활발히 진행되고 있다. 그러나 기존의 VCR-Index와 CQI-Index 기법은 질의영역을 셀 구조나 가상구조로 분할하여 처리하기 때문에 자원 및 연산을 공유 할 수 없어 질의 처리 속도가 현저히 저하되기 때문에 대량의 공간영역질의 처리에는 부적합하다. 그래서 본 논문에서는 공간영역질의의 효율적인 연산 공유를 위한 질의영역 밀집도 기반의 그룹화 기법을 제안한다. 이 기법은 질의영역의 밀집도를 이용하여 공간영역질의들을 그룹화 후 색인을 구성한다. 색인된 영역들의 데이터는 단일 큐로 구성 후 질의들의 프리디킷을 분석하여 자원 및 연산 공유기법을 통해 기존의 기법보다 처리 속도 향상 및 메모리 사용을 감소시켰다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.3
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• pp.69-75
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• 2011

In this paper, we propose an anycast event driven synchronization mechanism to reduce power overheads. Our proposed mechanism can reduce unnecessary polling operations on SHI(Snoop Hit Invalidate) or SHR(Snoop Hit Read) states. It prevents waisting bandwidth and reduces power overheads on polling operation. Also it decreases transition power of state change compared to broadcast model. Simulation results indicated that the proposed architecture had about 15.3% of power decrease compared to spin-lock model and about 4.7% of power decrease compared to broadcast model. Overall results indicated that proposed synchronization mechanism could increase power efficiency of multi-core system by reducing power overheads.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.461-476
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• 2003

Due to the implementation ease and alleviation of memory bottleneck effect, NUMA architecture has dominated in the multiprocessor systems for the past several years. However, because the NUMA system distributes memory in each node, frequent remote memory access is a key factor of performance degradation. Therefore, efficient design of RAC(Remote Access Cache) in NUMA system is critical for performance improvement. In this paper, we suggest Multi-Grain RAC which can adaptively control the RAC line size, with respect to each application behavior Then we simulate NUMA system with multi-grain RAC using MINT, event-driven memory hierarchy simulator. and analyze the performance results. At first, with profile-based determination method, we verify the optimal RAC line size for each application and, then, we compare and analyze the performance differences among NUMA systems with normal RAC, with optimal line size RAC, and with multi-grain RAC. The simulation shows that the worst case can be always avoided and results are very close to optimal case with any combination of application and RAC format.