• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.27-34
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• 2003

Recently, an efficient hardware development for a cryptosystem is concerned. The efficiency of a multiplier for GF($2^n$)is directly related to the efficiency of some cryptosystem. This paper, considering the trade-off between time complexity andsize complexity, proposes a new multiplier architecture having n[n/2] AND gates and n([n/2]+1)- $$\Delta$_n$ = XOR gates, where $$\Delta$_n$=1 if n is even, $$\Delta$_n$=0 otherwise. This size complexity is less than that of existing ${multipliers}^{[5][12]}$which are $n^2$ AND gates and $n^2$-1 XOR gates. While a new multiplier is a serial-parallel multiplier to output a result of multiplication of two elements of GF($2^n$) after 2 clock cycles, the suggested multiplier is more suitable for some cryptographic device having space limitations.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.143-146
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• 2001

본 논문에서는 다 채널 페이저 연산 장치를 전용하드웨어로 구현하기 위한 설계 구조에 대하여 제시하였으며, 이를 연산량이 많은 곱셈기를 시분할에 의해 공유하는 구조를 제시하였다. 또한 페이저 측정을 위한 Sliding-DFT 알고리즘을 순환 구현할 경우의 근사구현 오차에 관한 정량적인 연구를 수행하였다. 이러한 오차 영향의 해석을 기반으로 하여 곱셈기 공유 구조를 적용한 페이저 연산 장치를 설계하고, 설계한 하드웨어의 내부동작을 보여주는 시뮬레이션을 통해 설계의 정확성을 확인하였다

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.157-164
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• 2009

An efficient pipeline MDC Radix-4 FFT structure is proposed in this paper. Every stages in pipeline FFT structure consists of delay' commutator and butterfly. Proposed butterflies in front and rear stages utilize CORDIC and Common Sub-expression Sharing(CSS) techniques, respectively. It is shown that proposed butterfly structure can reduce the number of adders through sharing common patterns of CSD type coefficients. The Verilog-HDL modeling and Synopsys logic synthesis results that the proposed structure show 48.2% cell area reduction in the complex multiplication part and 22.1% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structures. Consequently, the proposed FFT structure can be efficiently used in various OFDM systems.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1365-1368
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• 2002

OFDM은 제4세대 변조기술로 일컬어지는 방식이다. 이는 최근 유럽에서 디지털 오디오 방송(DAB)과 디지털 비디오 방송(DVB)에 표준이 되었으며, IEEE 802.11a 무선 LAN 에서도 이 방식을 채택했고, ADSL, VDSL 등에서도 사용되어지고 있다. 본 논문에서는 이러한 OFDM 방식의 핵심이라고 할 수 있는 64포인트 FFT(Fast Fourier Transform)하드웨어 프로세서의 여러 가지의 구현된 예를 비교 분석하고, 가장 효율적인 방법인 Radix-2 SDF(Singlepath Delay Feedback)[1] 방법을 개선하여 새로운 구조를 제안하였다. 동일한 속도 성능을 가지는 여러구조 중에서 적은 수의 지연소자를 활용하여 FFT 크기를 작게 한 것이 SDF 방식으로 가장 널리 사용되고 있다. 본 논문에서는 SDF 방식이 내부적으로 4개의 복소곱셈기를 필요로 하는데 비해 2개의 복소곱셈기만을 사용하는 구조로 변형하고 컨트롤을 조절하여 새로운 구조를 설계하였다. 구현한 결과, FFT에서 전체 구조의 약 80%를 차지하는 복소곱셈기의 수를 절반으로 줄여 FFT 하드웨어 크기를 SDF 방식의 60% 정도로 줄일 수 있게 되었고, 이러한 구현방식은 64포인트 FFT만이 아닌 더 큰 크기의 FFT를 구현함에 있어서도 동일하게 적용할 수 있으며 현재 국내외에 발표된 논문 중 성능 대 면적비가 가장 우수한 구조이다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.703-705
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• 2001

본 논문에서는 셀룰라 오토마타(Cellular Automata, CA)를 이용한 MSB곱셈기를 제안한다. 본 논문에서 제안한 구조는 PBCA(Periodic Boundary CA)의 특성을 AOP의 특성과 조화시킴으로써 정규성을 높이고 시간지연을 줄일 수 있는 장점을 가지고 있다. 이 곱셈기는 지수연산을 위한 하드웨어 설계에 효율적으로 이용될 수 있을 것이다.